Patents Assigned to Siliconware Precision Industries Co., Ltd.
  • Publication number: 20240170355
    Abstract: An electronic package is provided, in which an electronic element is disposed on a carrier structure, and an interposer is stacked on the electronic element. Further, a wire is connected to the interposer and grounds the carrier structure, such that the wire and the interposer surround the electronic element. Therefore, the wire can be used as a shielding element when the electronic package is in operation to prevent the electronic element from being subjected to external electromagnetic interference.
    Type: Application
    Filed: February 24, 2023
    Publication date: May 23, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Ko-Wei CHANG, Chien-Cheng LIN
  • Publication number: 20240170415
    Abstract: An electronic package and a method thereof are provided, in which an electronic component, conductive structures and conductive components are disposed on one side of a carrier and electrically connected to the carrier. The electronic component, the conductive structures and the conductive components are encapsulated by an encapsulation layer. A shielding layer is formed on the encapsulation layer to cover the electronic component, where the shielding layer is electrically connected to the conductive structures and free from being electrically connected to the conductive components. A shielding structure is formed to cover the other side of the carrier.
    Type: Application
    Filed: April 11, 2023
    Publication date: May 23, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Ko-Wei CHANG, Chia-Yang CHEN
  • Publication number: 20240162101
    Abstract: An electronic package includes a first electronic element and a dummy die embedded in an encapsulation layer, where the dummy die is used to prevent a warpage caused by the mismatch of coefficient of thermal expansion (CTE) between the encapsulation layer and the first electronic element in the manufacturing process of large full-panel.
    Type: Application
    Filed: March 27, 2023
    Publication date: May 16, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventor: Yung-Ta LI
  • Publication number: 20240162180
    Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 16, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Feng Kao, Lung-Yuan Wang
  • Publication number: 20240162140
    Abstract: An electronic package is provided, in which an electronic structure used as an integrated voltage regulator and a plurality of conductive pillars are embedded in an encapsulating layer to facilitate electrical transmission with electronic components at a close range.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Feng Kao, Lung-Yuan Wang
  • Publication number: 20240162169
    Abstract: An electronic package is provided and includes a plurality of electronic elements, a spacing structure connecting each of the plurality of electronic elements, and a plurality of conductive elements electrically connected to the plurality of electronic elements and serving as external contacts. The spacing structure has a recess to enhance the flexibility of the electronic elements after the electronic elements are connected to one another, thereby preventing the problem of warpage. A method for fabricating the electronic package is also provided.
    Type: Application
    Filed: December 12, 2023
    Publication date: May 16, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Yuan-Hung Hsu, Chi-Jen Chen
  • Patent number: 11984379
    Abstract: Provided is an electronic package, in which a heat dissipating body is formed on an electronic device and is combined with a heat sink so that the electronic device, the heat dissipating body and the heat sink form a receiving space, and a heat dissipating material is formed in the receiving space and in contact with the heat sink and the electronic device, where a fluid regulating space is formed between the heat dissipating material and the heat dissipating body and is used as a volume regulating space for the heat dissipating material during thermal expansion and contraction.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: May 14, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chih-Ming Huang, Kuo-Hua Yu, Chang-Fu Lin
  • Patent number: 11984393
    Abstract: An electronic package is provided, in which an electronic structure used as an integrated voltage regulator and a plurality of conductive pillars are embedded in an encapsulating layer to facilitate electrical transmission with electronic components at a close range.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 14, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Feng Kao, Lung-Yuan Wang
  • Patent number: 11984412
    Abstract: An electronic package in which at least one magnetically permeable member is disposed between a carrier and an electronic component, where the electronic component has a first conductive layer, and the carrier has a second conductive layer, such that the magnetically permeable element is located between the first conductive layer and the second conductive layer. Moreover, a plurality of conductive bumps that electrically connect the first conductive layer and the second conductive layer are arranged between the electronic component and the carrier to surround the magnetically permeable member for generating magnetic flux.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: May 14, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Ko-Wei Chang
  • Publication number: 20240153884
    Abstract: An electronic package is provided, in which a first electronic element and a second electronic element stacked on each other are embedded in a cladding layer, a circuit structure electrically connected to the second electronic element is formed on the cladding layer, and a passive element and a package module are disposed on the circuit structure, so as to shorten the transmission distance of electrical signals between the package module and the second electronic element.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 9, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min FU, Hung-Kai WANG, Chi-Ching HO, Yih-Jenn JIANG, Yu-Po WANG
  • Publication number: 20240145372
    Abstract: A substrate structure is provided, in which an insulating protection layer is formed on a substrate body having a plurality of electrical contact pads, and the insulating protection layer has a plurality of openings corresponding to the plurality of exposed electrical contact pads, and the insulating protection layer is formed with a hollow portion surrounding a partial edge of at least one of the electrical contact pads at at least one of the openings, so as to reduce the barrier of the insulating protection layer.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Wen TSAO, Wen-Chen HSIEH, Yi-Lin TSAI, Hsiu-Fang CHIEN
  • Publication number: 20240145455
    Abstract: An electronic package is provided, in which an electronic module including a first electronic element and a second electronic element is disposed on a carrier structure embedded with a third electronic element, and the third electronic element is a photonic chip electrically connected to the electronic module. Therefore, with this configuration, it is beneficial to reduce a layout area of the carrier structure to meet the requirement of miniaturization.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Meng-Jie LEE, Chih-Nan LIN, Ci-Hong YAN, Nai-Hao KAO
  • Publication number: 20240145403
    Abstract: An electronic package is provided, in which electronic elements and at least one packaging module including a semiconductor chip and a shielding structure covering the semiconductor chip are disposed on a carrier structure, an encapsulation layer encapsulates the electronic elements and the packaging module, and a shielding layer is formed on the encapsulation layer and in contact with the shielding structure. Therefore, the packaging module includes the semiconductor chip and the shielding structure and has a chip function and a shielding wall function simultaneously.
    Type: Application
    Filed: February 6, 2023
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chih-Chiang HE, Ko-Wei CHANG, Chia-Yang CHEN
  • Publication number: 20240145398
    Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng-Liang HSU, Wan-Rou CHEN, Hsin-Yin CHANG, Tsung-Li LIN, Hsiu-Jung LI, Chiu-Lien LI, Fu-Quan XU, Yi-Wen LIU, Chih-Chieh SUN
  • Publication number: 20240145908
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, and an antenna structure is stacked on the carrier structure via conductors, where at least one through hole is formed on and penetrating through the antenna structure, and an insulating support body is formed between the carrier structure and the antenna structure, so that the insulating support body is correspondingly formed at the through hole and/or an edge of the antenna structure, and the through hole is free from being filled up by the insulating support body, such that the through hole has an air medium. The design of the through hole allows the characteristic of the dielectric constant of air being 1 to be utilized so as to reduce the signal loss and the signal offset, thereby facilitating the signal transmission of the antenna body.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Chun LAI, Hsuan-Jen WANG, Rung-Jeng LIN
  • Patent number: 11973043
    Abstract: An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: April 30, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Wen-Jung Tsai
  • Patent number: 11973014
    Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: April 30, 2024
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Fu Lin, Chin-Tsai Yao, Chun-Tang Lin, Fu-Tang Huang
  • Patent number: 11973047
    Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: April 30, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Feng Kao, Lung-Yuan Wang
  • Publication number: 20240136263
    Abstract: An electronic package is provided, in which a first electronic module and a second electronic module are stacked via a plurality of first conductive structures and a plurality of second conductive structures, and the amount of solder of the first conductive structures is greater than the amount of solder of the second conductive structures, such that the electronic package can be configured with the first conductive structures and the second conductive structures according to the degree of warpage of the electronic package, so as to effectively disperse the stress to avoid the problem of warpage.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 25, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hung-Kai WANG, Yih-Jenn JIANG, Don-Son JIANG, Yu-Lung HUANG, Men-Yeh CHIANG
  • Publication number: 20240128249
    Abstract: An electronic package is provided, in which a circuit structure is stacked on a carrier structure having a routing layer via support structures, where electronic elements are disposed on upper and lower sides of the circuit structure and the carrier structure, and the electronic elements and the support structures are encapsulated by a cladding layer, such that the electronic package can effectively increase the packaging density to meet the requirements of multi-functional end products.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 18, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Chi-Ching HO