Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerate SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.

Abstract: Systems and methods for providing a low power receiver device using fine grained time division are provided. In one embodiment, the receiver device comprises a tuner, a demodulator configured to demodulate at least one sampled signal, a payload processor configured to process at least one demodulated signal into an output format, and a time division control logic configured to generate a control signal to switch at least one component within the receiver device between modes to conserve power. The at least one component may be switched between an active mode, a standby mode, a power off mode, and a low power mode. In further embodiments, the at least one component may be switched between staggered modes.

Abstract: Digital logic circuitry is disclosed. The circuitry includes local oscillator drift and phase compensation logic that compensates the frequency drift and the phase noise of a local oscillator generated by a digitally controlled oscillator.

Abstract: Systems and methods for dynamically controlling an analog-to-digital converter (ADC) in order to conserve power are provided. In exemplary embodiments, a receiver device comprises a tuner configured to receive a signal, at least one programmable analog-to-digital converter (ADC), and a digital signal processing hardware comprising a control logic. The exemplary control logic is configured to generate a control signal to configure components within the receiver device to conserve power at the ADC.

Abstract: For each audio and data service, a table of contents (TOC) specifies which logical channel may carry data. The TOC may be transmitted over the NRSC-5 transmission system using a pre-defined protocol, which is received and decoded at an NRSC-5 receiver apparatus that extracts the TOC. When a user or an application requests a specific service from the receiver, the receiver logic may examine the TOC and may identify which LC may carry the requested service data. The receiver may only decode the LCs that are needed for the requested service, and may not decode other unneeded LCs thereby conserving power and memory.

Abstract: Systems and methods of decoding data streams and conserving power are described. In some embodiments, a stream of data containing audio and other data is divided into a plurality of timeslots. A first timeslot of the plurality of timeslots is allocated to a first service. A grant location message which indicates a location of the first timeslot allocated to the first service is generated. The grant allocation message and the plurality of timeslots are transmitted to a receiver. The receiver may receive and decode the grant allocation message to identify OFDM symbols that carry information regarding the first service. The receiver may also receive the plurality of timeslots. The receiver may set a power mode of a component during OFDM symbols that indicate a status of the first service.

Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerat SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.

Abstract: Systems and methods for providing a low power receiver device using fine grained time division are provided. In one embodiment, the receiver device comprises a tuner, a demodulator configured to demodulate at least one sampled signal, a payload processor configured to process at least one demodulated signal into an output format, and a time division control logic configured to generate a control signal to switch at least one component within the receiver device between modes to conserve power. The at least one component may be switched between an active mode, a standby mode, a power off mode, and a low power mode. In further embodiments, the at least one component may be switched between staggered modes.

Abstract: Systems and methods for dynamically controlling a tuner are provided. In exemplary embodiments, the tuner receives control signals generated by digital signal processing hardware (DSPHW). These control signals control noise figure and linearity characteristic of components within the tuner by adjusting a current supply to those components, according to a desired configuration determined by the DSPHW. As a result, the DSPHW can optimize power consumption of the tuner while allowing for sufficient tuner performance for reliable demodulation of received signals.

Abstract: Systems and methods for conserving power in a receiver device are provided. In exemplary embodiments, a receiver device comprises a tuner configured to receive a transmitted signal, at least one analog-to-digital converter (ADC), and a digital signal processing hardware comprising a control logic. The exemplary control logic is configured to determine if a symbol within the transmitted signal belongs to an erasure interval, and generate a control signal to configure a receiver device component to conserve power based on the determination.

Abstract: Systems and methods for providing a low power receiver device using fine grained time division are provided. In one embodiment, the receiver device comprises a tuner, a demodulator configured to demodulate at least one sampled signal, a payload processor configured to process at least one demodulated signal into an output format, and a time division control logic configured to generate a control signal to switch at least one component within the receiver device between modes to conserve power. The at least one component may be switched between an active mode, a standby mode, a power off mode, and a low power mode. In further embodiments, the at least one component may be switched between staggered modes.