Abstract: An apparatus comprising an amplifier comprising at least one amplifier transistor, a threshold detection network and a bypass capacitor. The amplifier may be configured to generate an output signal at a collector in response to an input signal received at a base. The threshold detection network may be coupled between the collector and the base of the amplifier transistor. The threshold detection network may include a bias transistor having a collector coupled to the collector of the amplifier transistor and an emitter coupled to the base of the amplifier transistor. The threshold detection circuit may be configured to (i) sense a feedback current and (ii) provide a DC signal to the base of the amplifier transistor for dynamically sourcing bias current to the amplifier. The bypass capacitor may be coupled to the base of the bias transistor.

Abstract: An apparatus comprising an amplifier circuit, a tuning circuit and a mixer circuit. The amplifier circuit may be configured to generate an output signal at a first node in response to an input signal received through a second node. A tuning circuit may be (i) coupled between said second node of the amplifier circuit and third node and (ii) configured to adjust an impedance presented to the third node in response to a tuning voltage. A mixer circuit may have a center tap coupled to the third node.

Abstract: An apparatus comprising a Darlington transistor pair and a bias circuit. The Darlington transistor pair may be configured to generate an output signal at an output node in response to an input signal received through an input node. The bias circuit may be coupled between an output transistor of said Darlington transistor pair and the input node. The bias circuit generally comprises (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of the bias transistor and base of the output transistor.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an intermediate signal in response to an input signal. The second circuit may be configured to generate a plurality of output signals in response to the intermediate signal. Each of the output signals may be (i) an amplified versions of the input signal and (ii) isolated between each of the other output signals.

Abstract: An apparatus comprising a Darlington transistor pair and a common-base transistor. The Darlington transistor pair may be configured to generate an output signal in response to an input signal. The common-base transistor may (i) be coupled between an output transistor of the Darlington transistor pair and the output signal and (ii) have a base configured to receive a frequency dependent reference voltage.

Abstract: An apparatus comprising a Darlington transistor pair and a bias circuit. The Darlington transistor pair may be configured to generate an output signal at an output node in response to an input signal received through an input node. The bias circuit may be coupled between an output transistor of said Darlington transistor pair and the input node. The bias circuit generally comprises (a) a bias transistor, (b) a bypass capacitor, and (c) a resistor connected between a base of the bias transistor and base of the output transistor.

Abstract: An apparatus comprising a Darlington transistor pair, a first common-base transistor and a second common-base transistor. The Darlington transistor pair may be configured to generate an output signal in response to an input signal. The first common-base transistor may be coupled between the Darlington transistor pair and the output signal. The second common-base transistor may also be coupled between the Darlington transistor pair and the output signal. The first and second common-base transistors may each have a base configured to receive a reference voltage.

Abstract: A microwave transistor structure having a step drain region comprising: (A) a substrate having a top surface; (B) a silicon semiconductor material of a first conductivity type, having a first dopant concentration and a top surface; (C) a conductive gate overlying and insulated from the top surface of the silicon semiconductor material; (D) at least one horizontal drain extension region of a second conductivity type and having a horizontal drain extension dopant concentration; (E) a step drain region formed in the silicon semiconductor material, and contacting the horizontal drain extension region; (F) a body region of the first conductivity type and having a body region dopant concentration; (G) a source region of the second conductivity type and having a source region dopant concentration; (H) a shield plate region formed on the top surface of the silicon semiconductor material over a portion of the horizontal drain extension region, the shield plate being adjacent and parallel to the horizontal drain extens

Abstract: A microwave transistor structure comprising: (1) a substrate having a top surface; (2) a silicon semiconductor material of a first conductivity type; (3) a conductive gate; (4) a channel region of a second conductivity type; (5) a drain region of the second conductivity type; (6) a body of the first conductivity type; (7) a source region of the second conductivity type; (8) a shield plate region formed on the top surface of the silicon semiconductor material over a portion of the channel region, wherein the shield plate is adjacent and parallel to the drain region, and to the conductive gate region; and (9) a conductive plug region formed in the body region of the silicon semiconductor material, wherein the conductive plug region connects a lateral surface of the body region to the top surface of the substrate.

Abstract: An apparatus for improving linearity of an RF signal comprising: (a) a splitter configured to receive an input RF signal, and configured to split the input RF signal into two RF signals comprising a first input RF signal, and a second input RF signal; (b) an over-biased non-linear RF power amplifier configured to receive the first input RF signal and configured to generate an over-biased non-linear output signal having an over-biased non-linear distortion component; (c) an under-biased non-linear RF power amplifier configured to receive the second input RF signal and configured to generate an under-biased non-linear output signal having an under-biased non-linear distortion component; and (d) a combiner configured to combine the over-biased non-linear output signal and the under-biased non-linear output signal, and configured to output the RF signal having substantially cancelled over-biased and under-biased distortion components.

Abstract: An apparatus comprising a Darlington transistor pair and a common-base transistor. The Darlington transistor pair may be configured to generate an output signal at an output node in response to an input signal received through an input node. The common-base transistor may be coupled between an output transistor of the Darlington transistor pair and the output node. The common-base transistor may have a base configured to receive a reference voltage.

Abstract: An apparatus for improving linearity of an RF signal comprising: (a) a splitter configured to receive an input RF signal, and configured to split the input RF signal into two RF signals comprising a first input RF signal, and a second input RF signal; (b) an over-biased non-linear RF power amplifier configured to receive the first input RF signal and configured to generate an over-biased non-linear output signal having an over-biased non-linear distortion component; (c) an under-biased non-linear RF power amplifier configured to receive the second input RF signal and configured to generate an under-biased non-linear output signal having an under-biased non-linear distortion component; and (d) a combiner configured to combine the over-biased non-linear output signal and the under-biased non-linear output signal, and configured to output the RF signal having substantially cancelled over-biased and under-biased distortion components.

Abstract: An RF circuit comprising: (a) an input low pass impedance transform network having an input and an output; (2)an input high pass impedance transform network having an input and an output; (3) an output high pass impedance transform network having an input and an output; and (4) an output low pass impedance transform network having an input and an output. The RF circuit includes an RF transistor coupled to the input high pass impedance transform network and to the output high pass impedance transform network. An input impedance of the RF transistor is matched to an input impedance of the RF circuit, wherein an output impedance of the RF transistor is matched to an output impedance of the RF circuit.

Abstract: A lateral RF MOS transistor with at least one conductive plug structure comprising: (1) a semiconductor material of a first conductivity type having a first dopant concentration and a top surface; (2) a conductive gate overlying and insulated from the top surface of the semiconductor material; (3) at least two enhanced drain drift regions of the second conductivity type of the RF MOS transistor; the first region laying partially underneath the gate; the second enhanced drain drift region contacting the first enhanced drain drift region, the dopant concentration of the second enhanced drain drift region is higher than the dopant concentration of the first enhanced drain drift region; (4) a drain region of the second conductivity type contacting the second enhanced drain drift region; (5) a body region of said RF MOS transistor of the first conductivity type with the dopant concentration being at least equal to the dopant concentration of the semiconductor epi layer; (6) a source region of the second conductivi

Abstract: A lateral RF MOS transistor with at least one conductive plug structure comprising: (1) a semiconductor material of a first conductivity type having a first dopant concentration and a top surface; (2) a conductive gate overlying and insulated from the top surface of the semiconductor material; (3) at least two enhanced drain drift regions of the second conductivity type of the RF MOS transistor; the first region laying partially underneath the gate; the second enhanced drain drift region contacting the first enhanced drain drift region, the dopant concentration of the second enhanced drain drift region is higher than the dopant concentration of the first enhanced drain drift region; (4) a drain region of the second conductivity type contacting the second enhanced drain drift region; (5) a body region of said RF MOS transistor of the first conductivity type with the dopant concentration being at least equal to the dopant concentration of the semiconductor epi layer; (6) a source region of the second conductivi

Abstract: An apparatus comprising an amplifier and a coupling circuit. The amplifier may be configured to generate an amplified output signal in response to a first input signal and a second input signal. The coupling circuit may be configured to generate the second input signal in response to the first input signal. The coupling circuit may be configured to increase a speed of propagation of the first input signal.

Abstract: An apparatus comprising an input stage, an output stage, a bias circuit and a feedback circuit. The input stage may be configured to generate a plurality of intermediate signals in response to an input signal. The output stage may be (i) DC coupled to the input stage and (ii) configured to generate an output signal in response to the intermediate signals. The output stage generally comprises a plurality of distributed amplifiers each configured to receive one of the intermediate signals. The bias circuit may be (i) connected between the input stage and the output stage and (ii) configured to adjust an input impedance of the input stage.

Abstract: Single and multiple ferrite crystal resonator, oscillator, and filter coupling structures are disclosed. In one embodiment, a single ferrite crystal resonator coupling structure is configured as a single pole YIG-tuned-oscillator (YTO) coupling structure. The YTO coupling structure includes a circuit substrate having an upper and a lower side. The circuit substrate includes an aperture extending through the circuit substrate between first and second openings on the upper and lower sides, respectively. The aperture is configured to permit rotation of a ferrite crystal disposable at least partially therein about a plurality of axes whereby a desirable axis of the ferrite crystal is alignable with a magnetic field within the aperture. At least one coupling line through which an electric current can be directed, which extends between a first end and a second end of the first opening of the aperture across at least a portion of the first opening of the aperture.

Abstract: A lateral RF MOS transistor with at least one conductive plug structure comprising: (1) a semiconductor material of a first conductivity type having a first dopant concentration and a top surface; (2) a conductive gate overlying and insulated from the top surface of the semiconductor material; (3) at least two enhanced drain drift regions of the second conductivity type of the RF MOS transistor; the first region laying partially underneath the gate; the second enhanced drain drift region contacting the first enhanced drain drift region, the dopant concentration of the second enhanced drain drift region is higher than the dopant concentration of the first enhanced drain drift region; (4) a drain region of the second conductivity type contacting the second enhanced drain drift region; (5) a body region of said RF MOS transistor of the first conductivity type with the dopant concentration being at least equal to the dopant concentration of the semiconductor epi layer; (6) a source region of the second conductivi

Abstract: An apparatus comprising a quadrature network, an RF combining circuit and a weighting network. The quadrature network may be configured to generate a first and a second signal in response to an input signal. The RF combining circuit may be configured to generate an output signal comprising the input signal variably phase shifted from a selectable fixed phase starting point in response to the first signal, the second signal and one or more weighting signals. The weighting network may be configured to generate the weighting signals in response to a voltage control signal and one of four possible output selections. The voltage control signal may be configured to control the variable phase shift.