Abstract: The present technology includes a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first semiconductor layer, a cell stack and a peripheral stack each disposed on the first semiconductor layer, a first slit structure extending in a first direction and penetrating the cell stack and the peripheral stack, a penetration structure penetrating the peripheral stack and being spaced apart from the first slit structure, and a support structure penetrating the peripheral stack. The support structure includes first sidewall portions spaced apart from each other and a second sidewall portion connecting the first sidewall portions to each other, and the penetration structure is disposed between the first sidewall portions.

Abstract: A semiconductor device and a method of manufacturing the same. The semiconductor device has a substrate in which recess regions are formed and semiconductor regions acting as a source region or a drain region is defined between the recess regions; a gate insulating layer disposed on an inner surface of each recess region; a recess gate disposed on the gate insulating layer in each recess region; an insulating capping layer disposed above the recess gate in each recess region; a metallic insertion layer disposed between a side surface of the recess gate and a side surface of the insulating capping layer and facing with a side surface of the source region or the drain region; and an intermediate insulating layer disposed between the metallic insertion layer and the recess gate to electrically insulate the metallic insertion layer from the recess gate.

Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a peripheral circuit disposed on a substrate; and a gate stack structure overlapping with the peripheral circuit. The gate stack structure includes a plurality of first cell plugs having substantially a cylindrical structure and a plurality of second cell plugs having substantially a hexagonal prism structure.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first and second vertical conductive patterns isolated from each other by a first slit. The semiconductor device may include at least one first half conductive pattern extending toward a first region disposed at one side of the first slit from the first vertical conductive pattern. The semiconductor device may include at least one second half conductive pattern extending toward a second region disposed at the other side of the first slit from the second vertical conductive pattern.

Abstract: In a method of treating a target film, a plurality of pattern structures with sidewall surfaces facing each other are provided. A target film is formed on the sidewalls of the plurality of pattern structures. A plurality of nanoparticles are distributed on the target thin film. The target thin film is thermally treated by irradiating laser light from upper sides of the plurality of pattern structures to the target thin film. The irradiated laser light is scattered from the plurality of nanoparticles.

Abstract: A memory device includes: a plurality of memory cells; soft read logic configured to generate soft data by reading data from the plurality of memory cells in response to a soft read command from a controller, the soft data including at least a major symbol and at least a minor symbol; a compressor configured to generate compressed data by: encoding, into a code alphabet having a second length, a major source alphabet including repetitions of the major symbol by a first length among a plurality of source alphabets included in the soft data, and encoding, into a code alphabet having a longer length than the second length, a minor source alphabet including repetitions of the major symbol by a shorter length than the first length and ending with one minor symbol; and an interface configured to provide the compressed data to the controller.

Abstract: A storage device performs a read operation, based on a temperature measured in a program operation or an erase operation. The storage device includes: a memory device including a plurality of memory blocks, the memory device measuring a temperature in a program operation or an erase operation; and a memory controller for setting an area in which the measured temperature is to be stored in the memory device, and controlling a read operation to be performed in the memory device. When a read command for a selected page among a plurality of pages included in each of the plurality of memory blocks is received from the memory controller, the memory device determines a read voltage and a pass voltage based on a temperature corresponding to the selected page and performs a read operation on the selected page by using the read voltage and the pass voltage.

Abstract: A semiconductor device includes an information update control circuit configured to generate a self-read pulse for a self-read operation, a self-write pulse for a self-write operation, and an information update section signal that is activated during an information update section when an active operation is performed, and a column control circuit configured to receive the self-read pulse and the self-write pulse, to generate a read column strobe pulse for outputting data or selection information data stored in a core circuit when the self-read operation is performed based on the self-read pulse or the read operation is performed according to the read pulse, and to generate a write column strobe pulse for storing the data or the selection information data in the core circuit when the self-write operation is performed based on the self-write pulse or the write operation is performed according to the write pulse.

Abstract: Provided is an image processing system and a disparity calculation method. An image processing device included in the image processing system includes a preprocessor configured to determine an effective range of a focal length of an image sensor based on first disparities measured at a plurality of focal lengths of an object having a fixed position from the image sensor, and determine a representative value of equivalent aperture values for the image sensor corresponding to the effective range based on the first disparities. The image processing device also includes a disparity calculator configured to calculate a second disparity of the target object within the effective range based on the focal length, a first distance, a second distance, and the representative value of the equivalent aperture values.

Abstract: A memory device includes adjacent first and second memory blocks, divided by a slit, in which a cell region and a connection region are divided in a direction perpendicular to the adjacent direction. The slit has a first width between the cell region of the first memory block and the cell region of the second memory block, has the first width between the connection region of the first memory block and the connection region of the second memory block, and has a second width wider than the first width in a region where the cell region and the connection region of the first memory block are adjacent to each other and the cell region and the connection region of the second memory block are adjacent to each other.

Abstract: A floating-point data operation circuit configured to perform an addition operation on first input data and second input data in floating-point format. The floating-point data operation circuit includes an exponent processing circuit configured to generate a number of first shift bits for first mantissa data of the first input data and a number of second shift bits for second mantissa data of the second input data using first exponent data of the first input data and second exponent data of the second input data. The exponent processing circuit includes an exponent subtraction circuit configured to generate and output exponent subtraction data by a subtraction operation and to generate and output a 2's complement of the exponent subtraction data, and a first selection output circuit configured to output first shift data and second shift data based on the most significant bit MSB value of the exponent subtraction data.

Abstract: A processing-in-memory (PIM) system includes a host including an identification (ID)-channel mapper configured to generate a channel address corresponding to an identification received from outside the PIM system, and a plurality of PIM controllers coupled to the host through a plurality of channels, and the plurality of PIM devices coupled to the plurality of PIM controllers through the plurality of channels.

Abstract: A processing-in-memory (PIM) device includes a processing-in-memory (PIM) device includes a memory bank including a left memory bank and a right memory bank, a first global buffer, a second global buffer, a left multiplying-and-accumulating (MAC) operator configured to perform a MAC operation on a first set of a plurality of weight data and a first set of a plurality of vector data, a right MAC operator configured to perform the MAC operation on a second set of the plurality of the weight data and a second set of the plurality of the vector data, and a bias data converter configured to receive bias input data and output bias output data, wherein the bias output data includes a range of numbers that is increased over a range of numbers of the bias input data and includes a value equal to half the value of the bias input data.

Abstract: A memory device includes memory cells connected to a selected word line; a peripheral circuit configured to perform a first program operation of programming a threshold voltage of each of memory cells to a pre-threshold voltage less than a target threshold voltage, and perform a second program operation of programming the threshold voltage of each of the memory cells to the target threshold voltage after the first program operation is performed; and control logic configured to control the peripheral circuit so that a first pass voltage and a second pass voltage are sequentially applied to adjacent word lines, when a program voltage is applied to the selected word line, in the first program operation and the second program operation. A magnitude of the second pass voltage in the first program operation may be greater than a magnitude of the second pass voltage in the second program operation.

Abstract: A memory system may include: a memory device including a plurality of memory blocks; and a memory controller configured to receive a write request including a logical address from an outside, to store write data corresponding to the write request in a first memory block among the plurality of memory blocks, wherein when a map information update is required and the write request is a sequential write operation, to store, in a second memory block, offset information related to a page of the first memory block in which the write data is lastly stored.

Abstract: A memory device, and an operating method of the memory device, includes a plurality of memory cells connected between word lines and bit lines and a voltage generator for generating a program voltage or a pass voltage, which is applied to the word lines. The memory device also includes a page buffer group for applying program allow voltages or a program inhibit voltage to the bit lines and a control circuit for controlling the voltage generator and the page buffer group in response to a command. In a program operation of selected memory cells connected to a selected word line among the word lines, the control circuit controls the page buffer group such that the program allow voltages are increased stepwise according to a number of program loops performed on the selected memory cells.

Abstract: A first impedance calibration part configured to perform a first impedance calibration operation of generating a first impedance calibration code set for adjusting an impedance of a first terminating resistor to a first target value, with reference to an external resistor having a first resistance value. A second impedance calibration part configured to perform a second impedance calibration operation of generating a second impedance calibration code set for adjusting an impedance of a second terminating resistor to a second target value, with reference to a reference resistance unit, a resistance value of which is set to a second resistance value according to a part of the first impedance calibration code set.

Abstract: Provided herein may be an image sensor and a signal conversion method. A signal transducer for converting an analog pixel signal into a digital signal may include an operational amplifier configured to receive a pixel signal, a conversion gain of which is changed, through a first input terminal, receive a ramp signal through a second input terminal, and change polarities of the first input terminal and the second input terminal based on an inverse signal, and a signal manager configured to generate the inverse signal in response to a change in the conversion gain and transfer the inverse signal to the operational amplifier.

Abstract: A semiconductor device includes gate structures including conductive layers extending in a first direction; channel structures located in the gate structures and protruding from surfaces of the gate structures; a slit structure located between the gate structures and including a protrusion that protrudes from the surfaces of the gate structures; and a compressive stressor connected to the protrusion of the slit structure and extending in the first direction.

Abstract: A color matching circuit of an image sensor includes a receiving end configured to receive an analog pixel signal. The color matching circuit also includes a path controller including a first switch set configured to control current paths between a common node coupled to the receiving end and power sources and a second switch set configured to control signal paths between the common node and analog-to-digital converters, the path controller being configured to determine on-off states of switches included in the first switch set and the second switch set based on a color corresponding to the analog pixel signal. The path controller transfers the analog pixel signal to a target analog-to-digital converter determined depending on the on-off states of the switches, among the analog-to-digital converters.