Abstract: A method of handling an error correcting code (ECC) in a non-volatile memory includes performing a first ECC operation on data codes to generate first parity codes; compressing the first parity codes to generate compressed parity codes; performing a second ECC operation on the compressed parity codes to generate additional parity codes; and writing the data codes, the compressed parity codes and the additional parity codes into a memory unit of the non-volatile memory.

Abstract: A method of accessing an on-chip read only memory (ROM) includes dividing a frequency of a system clock by a specific divisor, in order to generate a ROM clock; combining a specific number of adjacent addresses into a combined address, wherein the specific number is determined according to the specific divisor; inserting a first stall signal into a real output data, wherein a length of the first stall signal is determined in order to meet a timing requirement for accessing the on-chip ROM; generating an output data of the on-chip ROM according to the combined address, wherein a width of the output data is extended by a specific multiple which is determined according to the specific number; and generating a first delay corresponding to the length of the first stall signal in the address.

Abstract: A micro secure digital (SD) adapter, for adapting a micro SD card to an SD interface, the micro SD adapter comprising a micro SD slot, for disposing the micro SD card; a pin module, comprising a plurality of signal pins, a first ground pin, and a second ground pin; a plurality of connectors, for conducting the plurality of signal pins and the first ground pin to the micro SD card according to a pin configuration of the micro SD card when the micro SD card is disposed in the micro SD slot; and a conducting module, electrically connected between a terminal of a first connector corresponding to the first ground pin and the second ground pin.

Abstract: A system and method for programming a multi-bit per cell non-volatile memory with padding data is disclosed to program at least one less-significant-bit (LSB) page with padding data while programming host data in the multi-bit per cell non-volatile memory, in a manner such that a more-significant-bit (MSB) page corresponding to each LSB page programmed with host data of the same write command is programmed with host data.

Abstract: A method of scheduling a plurality of tasks for a plurality of memories in a memory system is disclosed. The method includes classifying each task among the plurality of tasks to a task type among a plurality of task types, disposing a plurality of task queues according to the plurality of task types wherein each task queue stores tasks to be executed within the plurality of tasks, assigning a priority for each task type among the plurality of task types, disposing at least one execution queue; and converting a first task stored in a first task queue among the plurality of task queues into at least one command to be stored in a first execution queue among the at least one execution queue, wherein the at least one command is executed according to the priority of a first task type corresponding to the first task queue.

Abstract: A delay device for generating a signal for a random component in a random number generator is disclosed. The delay device includes a delay module, for generating a plurality of delayed signals, wherein each delayed signal has a delay time and the delay time is different from each other; a first multiplexer, coupled to the delay module, for outputting a delayed signal among the plurality of delayed signals as a delayed trigger signal to control the random component to generate a random bit; and a delay selector, coupled to the first multiplexer, for generating a selecting signal to control the first multiplexer to select to output the delayed signal as the delayed trigger signal.

Abstract: In a system and method of enhancing data reliability, a reference value associated with error count is obtained, and an error count of data stored in a buffer is obtained whenever an event is triggered. An accumulated value associated with error counts is acquired when the recorded error count is greater than an error threshold value. System slowdown is performed when the accumulated value is greater than a predetermined value.

Abstract: A method of accessing data in a multi-layer cell (MLC) memory includes using single-layer cell (SLC) configuration to transfer a portion of a plurality of memory units in the MLC memory to an SLC area to form a plurality of MLC memory units and a plurality of SLC memory units; storing data in the plurality of SLC memory units when the data is assigned to be stored in an MLC memory unit; mapping the MLC memory unit to the SLC memory units; reading the data by obtaining the data in the SLC memory units corresponding to the MLC memory unit; and reallocating the SLC memory units to use MLC configuration when an update of data is involved in the MLC memory unit or a new data is assigned to be stored in at least one of the SLC memory units.

Abstract: A method of writing data in a non-volatile memory includes writing data from a first memory unit to a second memory unit of the non-volatile memory; checking a health of the second memory unit to generate a health result; and reserving the data in the first memory unit and mapping information corresponding to the first memory unit when the health result indicates that the second memory unit is unhealthy.

Abstract: A method of sorting a multi-bit per cell non-volatile memory includes programming and reading to test an n-bit-per-cell (n-bpc) non-volatile memory, which has a plurality of m-bpc pages, where m is a positive integer from 1 through n. If the m-bpc page fails the test, counting a block associated with the failed m-bpc page to (m-1)-bpc blocks, wherein each said m-bpc page is subjected to at most one time of programming and reading. When m is equal to 1, the 0-bpc block corresponds to a bad block.

Abstract: By assigning a slave unit and at least one master unit in a buffer controller, clocks of the at least one master unit can be unified with a clock of the slave unit. A buffer status array is assigned for the slave unit in a buffer, and either a range status array or a queue status array is assigned for the master unit in the buffer for performing operations of the buffer controller in an accessing-by-block manner or in an accessing-by-spaced-interval manner. The master unit cooperated with the slave unit is determined from the at least one master unit by using a starvation-preventing algorithm.

Abstract: A time-sharing buffer access system manages a buffer among plural master devices. Plural buffer handling units are operable to associatively couple the master devices, respectively, and a first end of each buffer handling unit is used to independently transfer data to or from the associated master device. A second end of each buffer handling unit is coupled to a buffer switch. A time slot controller defines a time slot, during which one of the buffer handling units is selected by the buffer switch such that data are only transferred between the selected buffer handling unit and the buffer.

Abstract: A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data.

Abstract: A method of accessing an on-chip read only memory (ROM) includes dividing a frequency of a system clock by a specific divisor, in order to generate a ROM clock; combining a specific number of adjacent addresses into a combined address, wherein the specific number is determined according to the specific divisor; inserting a first stall signal into a real output data, wherein a length of the first stall signal is determined in order to meet a timing requirement for accessing the on-chip ROM; generating an output data of the on-chip ROM according to the combined address, wherein a width of the output data is extended by a specific multiple which is determined according to the specific number; and generating a first delay corresponding to the length of the first stall signal in the address.

Abstract: The present invention is directed to a bit-level memory controller and method adaptable to managing defect bits of a non-volatile memory. A bad column management (BCM) unit retrieves a bit-level mapping table, in which defect bits are respectively marked, based on which the BCM unit constructs a bit-level script (BLS) that contains a plurality of entries denoting defect-bit groups respectively. An internal buffer is configured to store data managed by the BCM unit according to the BLS.

Abstract: A method of dynamically adjusting a mapping manner for a non-volatile memory includes mapping a plurality of logical addresses to a plurality of physical addresses by a first mapping unit; storing data in the non-volatile memory by the first mapping unit; and mapping at least one logical address to at least one physical address by a second mapping unit according to the stored data.

Abstract: A method of managing a non-volatile memory where the non-volatile memory comprises a plurality of memory blocks and each of the plurality of memory blocks includes a plurality of memory pages includes partitioning a memory page among the plurality of memory pages into a plurality of clusters; and writing data and a mapping information corresponding to the data into different clusters of the plurality of clusters.

Abstract: In a system and method of enhancing data reliability, a reference value associated with error count is obtained, and an error count of data stored in a buffer is obtained whenever an event is triggered. An accumulated value associated with error counts is acquired when the recorded error count is greater than an error threshold value. System slowdown is performed when the accumulated value is greater than a predetermined value.

Abstract: A method of accessing a non-volatile memory is disclosed. Original bits of data are duplicated on a bit level to generate a plurality of duplicated bits corresponding to each original bit. At least one shielding bit is provided between the duplicated bits corresponding to different original bits. The duplicated bits and the at least one shielding bit are programmed to the non-volatile memory. The original bits are generated or determined according to the duplicated bits.

Abstract: An exemplary embodiment of the present disclosure illustrates an automated mass production method, adapted for an automated mass production system in manufacturing at least an electronic device having a storage unit, the method includes steps of: determining a protocol type of the Auto Handler to select one of the agents; establishing a first communication protocol communication between the MP tool module and the selected agent; establishing a second communication protocol communication between the selected agent and the Auto Handler; the Auto Handler outputting a processing command to the selected agent; the selected agent converting the processing command into a MP tool module executable MP tool instruction; and the selected agent outputting the corresponding MP tool instruction to the MP tool module so as to have the MP tool module executed the MP tool instruction to automatically perform a corresponding mass production process to the electronic device.