Abstract: A SRAM on an SOI substrate comprising a network of rows and columns of 6T memory cells with two inverters and two switch transistors, each cell being connected to two bit lines and to one of the word lines. Each memory cell comprises two first regions of the first conductivity type, each first region comprising the drains or the sources of first and third transistors, and being in contact with a second region of the second conductivity type comprising the drain or the source of a second transistor, the first and second regions being short-circuited by a conductive material, the conductive tracks of the first level taking part in the interconnections between the inverters, and in the interconnections between the switch transistors and the word line being parallel to the bit lines.

Abstract: A SRAM on an SOI substrate comprising a network of rows and columns of 6T memory cells with two inverters and two switch transistors, each cell being connected to two bit lines and to one of the word lines. Each memory cell comprises two first regions of the first conductivity type, each first region comprising the drains or the sources of first and third transistors, and being in contact with a second region of the second conductivity type comprising the drain or the source of a second transistor, the first and second regions being short-circuited by a conductive material, the conductive tracks of the first level taking part in the interconnections between the inverters, and in the interconnections between the switch transistors and the word line being parallel to the bit lines.