Abstract: A method for managing a writing operation for a multi-level cell (MLC) nonvolatile memory by a host is provided. The MLC nonvolatile memory has a plurality of MLC blocks, each MLC cell of each MLC block can store multiple logical data bits. The method includes forming a turbo writing unit from the spare block pool; writing a data sent by the host to the turbo writing unit; and changing the role of the turbo writing unit into a turbo data unit. The turbo writing unit is formed with at least one of the MLC blocks, each MLC cell of the at least one of the MLC blocks stores a portion of the logical data bits the MLC cell is capable of storing.

Abstract: A microelectromechanical system (MEMS) device includes a diaphragm capacitor, connected between a capacitor biasing voltage source and a ground. A source follower circuit is coupled to the diaphragm capacitor. An amplifier is coupled to the source follower circuit to amplify the voltage signal as an output voltage signal. A programmable trimming circuit is implemented with the amplifier to trim a gain or implemented with the capacitor biasing voltage source to trim voltage applied on the diaphragm capacitor. Whereby, the output voltage signal has a target sensitivity.

Abstract: The present invention provides a data cache architecture interposed between a host and a flash memory, the data cache architecture comprising: a buffer memory, receiving data from the host; a memory controller, deploying the data in the buffer memory; and a data cache memory, controlled by the memory controller according to a cache algorithm. The data cache architecture and the cache algorithm used in the data cache architecture can be used to minimize the program/erase count of the NAND type flash device.

Abstract: A micro-electro-mechanical systems (MEMS) device includes a back-plate substrate, having an intended region formed with a plurality of perforating holes. A first structural dielectric layer, disposed on the back-plate substrate, wherein the dielectric layer having an opening above the intended region. An etching stop layer, disposed over the first structural dielectric layer. A second structural dielectric layer, formed over the back-plate substrate. The etching stop layer and the second structural dielectric layer form at least a part of a micro-machine diaphragm, and cover over the opening of the first structural dielectric layer to form a chamber between the micro-machine diaphragm and the back-plate substrate.

Abstract: A USB audio controller includes an USB interface unit, an audio interface unit, a storage interface unit, and a processing unit. The USB interface unit is used to connect to a USB bus for communicating with a host by a communication information. The audio interface unit is used to connect to at least one audio device for communicating with an audio signal. The storage unit is used to connect to a memory unit for communicating storage information. The processing unit is for processing the communicating information and audio signal.

Abstract: An USB audio controller includes an USB interface unit, an audio interface unit, a storage interface unit, and a processing unit. The USB interface unit is used to connect to an USB bus for communicating with a host by a communication information. The audio interface unit is used to connect to at least one audio device for communicating with an audio signal. The storage interface unit is used to connect to a memory unit for communicating storage information. The processing unit is for processing the communicating information, storage information, or audio signal.

Abstract: A micro-electro-mechanical system (MEMS) device includes a substrate, having a first side and second side, the second side has a cavity and a plurality of venting holes in the substrate at the second side with connection to the cavity. However, the cavity is included in option without absolute need. A structural dielectric layer has a dielectric structure and a conductive structure in the dielectric structure. The structural dielectric layer has a chamber in connection to the cavity by the venting holes. A suspension structure layer is formed above the chamber. An end portion is formed in the structural dielectric layer in fix position. A diaphragm has a first portion of the diaphragm fixed on the suspension structure layer while a second portion of the diaphragm is free without being fixed.

Abstract: A micro-electro-mechanical systems (MEMS) package includes a MEMS microphone device. The MEMS microphone device has a first substrate and at least a sensing element on the first substrate wherein a first chamber in the MEMS microphone device is connected to the sensing element. A second substrate is disposed over the MEMS microphone device to provide a second chamber in the second substrate over the sensing element opposite to the first chamber.

Abstract: The present invention provides a MEMS device, be implemented on many MEMS device, such as MEMS microphone, MEMS speaker, MEMS accelerometer, MEMS gyroscope. The MEMS device includes a substrate. A dielectric structural layer is disposed over the substrate, wherein the dielectric structural layer has an opening to expose the substrate. A diaphragm layer is disposed over the dielectric structural layer, wherein the diaphragm layer covers the opening of the dielectric structural layer to form a chamber. A conductive electrode structure is adapted in the diaphragm layer and the substrate to store nonvolatile charges.

Abstract: A micro-electro-mechanical systems (MEMS) device includes a back-plate substrate, having an intended region formed with a plurality of perforating holes. A first structural dielectric layer, disposed on the back-plate substrate, wherein the dielectric layer having an opening above the intended region. An etching stop layer, disposed over the first structural dielectric layer. A second structural dielectric layer, formed over the back-plate substrate. The etching stop layer and the second structural dielectric layer form at least a part of a micro-machine diaphragm, and cover over the opening of the first structural dielectric layer to form a chamber between the micro-machine diaphragm and the back-plate substrate.

Abstract: The present invention provides a data cache architecture interposed between a host and a flash memory, the data cache architecture comprising: a buffer memory, receiving data from the host; a memory controller, deploying the data in the buffer memory; and a data cache memory, controlled by the memory controller according to a cache algorithm. The data cache architecture and the cache algorithm used in the data cache architecture can be used to minimize the program/erase count of the NAND type flash device.

Abstract: A memory storage device includes a host interface to be connected to a terminal host, a controller connected to the host interface, and a fingerprint sensor and a memory module both connected to the controller. The controller communicates with the terminal host by handshakes and causes the terminal host to automatically run a suitable driver and a suitable application program from the memory module to the terminal host. The terminal host receives an instruction from a user through the driver and the program and informs the controller to control the fingerprint sensor to read to-be-recognized fingerprint data of the user. The terminal host utilizes the application program to process and judge whether or not the to-be-recognized fingerprint data substantially matches with template fingerprint data stored in the memory module, and further enables a specific block of the memory module to be accessed by the terminal host according to a matching result.

Abstract: An audio playback apparatus is based on a pre-defined data communication protocol, and communicating with an external host. The audio playback apparatus includes an audio playback engine, having a plurality of I/O pins based on the pre-defined data communication protocol for communicating with the external host. The pre-defined data communication protocol allows to transmit a communication information between the audio playback engine and the external host. In addition, an audio control command and an audio data stream defined in a pre-defined protocol are treated as the communication information between the audio playback engine and the external host.

Abstract: A method of state maintenance for a flash storage card system. The method includes using a plurality of signals, including a working voltage signal, a low voltage detection (LVD) signal, an LVD interrupt signal, a firmware polling signal, an LVD interrupt reset signal. The LVD signal responds to a voltage level of the working voltage at a preset voltage level. The LVD interrupt signal responds to the level of the LVD signal. After the LVD signal returns to the high level state and the firmware polling signal does the polling action to the LVD interrupt signal, then the LVD interrupt reset signal is issued to reset the LVD interrupt signal.

Abstract: An internet phone system is implemented in a computer system, including an internet-phone software unit, for storing a software used by the computer system to operate as an internet phone. An audio-file storage software unit is for storing a plurality of audio files. A USB (Universal Serial Bus) audio interface software unit is coupled with the internet-phone software unit and the audio-file storage unit. A USB audio apparatus is coupled to the audio interface unit, and comprising at least a microphone and a speaker. Wherein, the USB audio interface unit stores a software for selecting one of the audio files to serve as the phone-call ring, and for driving the speaker in the USB audio apparatus by the computer system for generating ringing sound for an incoming call.

Abstract: An access time adjusting circuit is used in a non-volatile memory to obtain an optimized access time in operation. The circuit includes an access time detecting unit, used to detect a performance status of the non-volatile memory under an operation clock and output the performance status. An access time controlling unit is used to generate at least one adjusting operation clock. Each adjusting operation clock serves as the operation clock for the non-volatile memory. In addition, the non-volatile memory, the access time controlling unit, and the access time detecting unit are connected to form a detection and adjustment loop, so that an optimized operation clock is determined after checking the at least one adjusting operation clock.

Abstract: A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.

Abstract: A measure system for signal measurement is introduced. The measure system simplifies the effort for a signal measurement in many applications. The application for a signal measurement is, for example, computation of a signal average value. The measure system includes a digital computation circuit together with an analog to digital converter (ADC) to constitute a compact signal measurement component. With the proposed design, a general microcontroller can proceed with a signal level sense and control with very few CPU power. In addition, the proposed system can be integrated with other analog or digital signal processing circuitry to form a single silicon chip.

Abstract: A method for fabricating non-volatile memory on a substrate includes forming a plurality of doped lines in the substrate along a first direction, wherein the doped lines serve as a plurality of bit lines, and portions of each of the doped lines serves as source/drain regions for a plurality of memory cells. A charge storage stacked layer is formed over the substrate, wherein the charge storage stacked layer includes a charge trapping layer. A conductive layer is formed over the charge storage layer. The conductive layer and the charge storage stacked layer are patterned to form a plurality of word lines along a second direction, intersecting with the first directing. The remaining portion of the charge trapping layer is just under the word lines, not covering the isolation region between the word lines.

Abstract: An access time adjusting circuit is used in a non-volatile memory to obtain an optimized access time in operation. The circuit includes an access time detecting unit, used to detect a performance status of the non-volatile memory under an operation clock and output the performance status. An access time controlling unit is used to generate at least one adjusting operation clock. Each the adjusting operation clock serves as the operation clock for the non-volatile memory. In addition, the non-volatile memory, the access time controlling unit, and the access time detecting unit are connected to form a detection and adjustment loop, so that an optimized operation clock is determined after checking the at least one adjusting operation clock.