Abstract: A digital pattern generator generates various kinds of digital pattern signals. A first memory stores an execution signal, an area control signal and a digital pattern. A program counter generates a first address signal in accordance with the execution signal read from the first memory and a first clock signal, and the first memory is addressed by the first address signal. Thus, the pattern generator operates as a microprogram type generator. A second memory includes a plurality of memory areas each storing a digital pattern, and a capacity of each the memory area corresponds to that of the first memory. When the second memory is addressed by a second address signal from an address counter, the pattern generator operates as a sequential type generator. When the memory area of the second memory is selected by the area control signal read from the first memory and the selected memory area is addressed by the first address signal, the second memory acts as an auxiliary memory of the first memory.

Abstract: A digital signal delay circuit which delays a plurality of digital input signals by a use of a single delay device group and a plurality of delay sections is disclosed. The delay device group generates a plurality of different phase clock signals. Each of the delay sections includes selection means for selecting one of the clock signals from the delay device group and latch means for latching the digital input signal in response to the output signal from the selection means. The output signal from the latch means is the delayed input signal, and a delay time is controlled by the selection means. The delay device group is used in common for the plurality of delay sections, so that the digital signal delay circuit is simple and inexpensive in construction.

Abstract: A logic analyzer is disclosed which displays at least an input logic signal on a cathode ray tube, controls a cursor position on the cathode ray tube and obtains a relationship between a predetermined phenomenon included in the input logic signal and the cursor position. In a search mode, the predetermined phenomenon is a search word or a glitch. In a compare mode, the predetermined phenomenon is a reference logic signal.

Abstract: In a method for testing for probe calibration, a square-wave signal is applied to a probe and a cyclic probe output signal resulting therefrom is compared to a reference level at a plurality of points along one cycle of the output signal. The reference signal is iteratively increased or decreased until it is less than or greater than a minimum or maximum peak magnitude of the probe output signal by a small amount. The probe is then determined to be calibrated according whether the magnitude of the output signal at each point is greater than or less than the reference level.

Abstract: A digital logic signal characterized by a bit sequence is displayed on a raster scan type screen in compressed form. The bit sequence is divided into N+1 bit segments and each bit of each segment, excluding the first bit of each segment, is compared to its preceding bit on a bit-by-bit, segment-by-segment basis. If a bit matches its preceding bit, a bit matching the preceding bit is generated. If a bit does not match its preceding bit, a bit opposite in state to the last bit produced is generated. The generated bits thus comprise a compressed sequence of N bit segments each corresponding to one N+1 bit segment of the original data sequence. A compressed waveform based on the generated sequence is then displayed.

Abstract: A circuit detects that a plurality of signals are generated in a predetermined sequence. The plurality of signals are applied to address terminals of a memory which has stored therein a predetermined pattern, and a divide-by-N counter (N:positive integer) counts a first data output signal from the memory N times and applies a carry output signal generated as a result thereof to another address terminal of the memory. An output signal of the circuit is derived from a second data output terminal of said memory when the plurality of input signals occur in the predetermined pattern of the memory and the carry signal from the counter is applied to the memory.

Abstract: An apparatus for diagnosing a plurality of digital-to-analog converters simultaneously is provided. Digital signal generation means applies digital signals to the plurality of digital-to-analog converters, and the digital signals are changed in sequence so that the analog outputs from the converters are changed symmetrically with respect to a first predetermined value. The analog outputs from the converters are combined by a resistor network, and the combined output is compared with a second predetermined value by a comparator. If the comparator's output is kept to a predetermined level regardless of changing the digital signals, the digital-to-analog converters are judged that they operate properly.

Abstract: A set point control method and apparatus for controlling many set points of an electronic apparatus by using a simple switch is disclosed. A switch condition is repeatedly detected, and a difference of the switch conditions is obtained when a former switch condition is different from the present switch condition. If a switch is a rotary digital switch for selecting one of a plurality of digital words, the difference is defined by the rotation direction of the switch and a difference of the former and present digital words. A memory stores a plurality of set information, and is addressed in accordance with the difference for controlling the set point of the electronic apparatus.

Abstract: An apparatus for displaying logic signals on a raster scan type display device is disclosed. A memory circuit stores a plurality of basic patterns corresponding to segments of a logic waveform. The basic patterns are selected from the memory circuit in accordance with the logic signal and are applied to an edge generator for generating an intensity control signal for varying the intensity of an electron beam generated within the raster scan type display device.