Abstract: A pre-drive circuit with an output buffer that may contain a bootstrap circuit is described. The bootstrap circuit may be configured to output a voltage level greater in magnitude than the supply voltage that the bootstrap circuit is coupled with. The pre-drive circuit may contain a timing circuit. The timing circuit may be configured to at least partially determine when the bootstrap circuit outputs a voltage greater in magnitude than the supply voltage. The pre-drive circuit may also contain a pre-drive buffer circuit. This pre-drive buffer circuit may be capable of three outputs: (1) logical zero, or roughly electrical ground; (2) logical one, or roughly the level of the voltage supply, and (3) an outputted voltage greater than the voltage supply.

Abstract: A standby regulator circuit includes a standby bias circuit and a standby operational amplifier. The standby regulator circuit provides a standby regulated control voltage to a multiplexer. A regular operational amplifier provides a regulated control voltage to the multiplexer. During regular operation, the multiplexer selects the regular operational amplifier and selects the standby regulator circuit in a low-power mode. The multiplexer couples to a native pass transistor gate having a threshold voltage about equal to 0 V. The native pass transistor provides a regulated output voltage with relatively low-level input control voltages. In low-power mode, a power-down signal, provided to the multiplexer, smoothly transitions regulated control voltage from the regular operational amplifier to regulated control voltage sourcing from the standby operational amplifier.

Abstract: Methods, systems, and devices are described for the implementation of a novel architecture to support download sequencing techniques for circuit configuration data. Sets of configuration data from nonvolatile memory may be sequentially transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Different programmable circuit elements may use configuration data, but have different ramp-up times before stable operation. With early download sequence positioning of configuration data, and corresponding immediacy in initiation of operation, certain clock elements are able to commence initiation of operation while remaining clock elements are provided with configuration data from a latter portion of the download sequence.

Abstract: A distributed signal multiplexer circuit programmably routes electronic signals. The circuit includes at least two distributor subcircuits. Each distributor subcircuit is configured to connect an input port to an output port through a switch, with a state of each switch being controlled by information received at a control port. The first and second distributor subcircuits are part of a first and second power domain, respectively. The distributed multiplexer circuit also includes an aggregator subcircuit. The aggregator subcircuit is configured to have a first input port connected with the output port of the first distributor subcircuit, a second input port connected to the output port of the second distributor subcircuit, and the output port signal being a signal selected from among the signals received at the input ports of the distributor subcircuits.

Abstract: Methods, systems, and devices are described for the implementation of a novel architecture to support a calibrated rate for the transfer of circuit configuration data. Sets of configuration data from a memory may be transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Upon system power-up, there may be a default speed for the transfer of the configuration data. Techniques are described to first transfer calibration data upon power-up; the transferred calibration data may then be used to set an accelerated speed for a remaining portion of the transfer.

Abstract: Methods, systems, and devices are described for a power-on sequence for a circuit. A sequence generator for an electronic system may control various power domains to enter known states and prevent unwanted states as other domains of the system power-up. Regulator modules may be controlled to remain in an inoperable state until a reference voltage stabilizes at a predetermined reference level. The regulator modules regulate a received voltage supply to output a regulated voltage at the reference level, the regulated voltage set via a comparison to the reference voltage. Various analog and digital modules may be controlled to remain in an known state until the regulated voltage stabilizes at substantially the reference level. Additional sequencing is described for other dependencies, as well.

Abstract: A standby regulator circuit includes a standby bias circuit and a standby operational amplifier. The standby regulator circuit provides a standby regulated control voltage to a multiplexer. A regular operational amplifier provides a regulated control voltage to the multiplexer. During regular operation, the multiplexer selects the regular operational amplifier and selects the standby regulator circuit in a low-power mode. The multiplexer couples to a native pass transistor gate having a threshold voltage about equal to 0 V. The native pass transistor provides a regulated output voltage with relatively low-level input control voltages. In low-power mode, a power-down signal, provided to the multiplexer, smoothly transitions regulated control voltage from the regular operational amplifier to regulated control voltage sourcing from the standby operational amplifier.

Abstract: A rail-to-rail operational amplifier has a pair of input terminals and an output terminal, and includes first and second parallel-connected differential input stages configured to generate a differential output signal OUTN, OUTP in response to a differential input signal VINN, VINP received at the pair of input terminals. Each of the first and second differential input stages in turn includes a pair of source-follower transistors and a pair of bulk-driven transistors. The pair of source-follower transistors are respectively coupled between the pair of input terminals and a bulk terminal of the pair of bulk-driven input transistors. Further, the pair of source-follower transistors in the first differential input stage have a different threshold voltage than the source-follower transistors in the second differential input stage.

Abstract: Embodiments provide systems and methods for supporting reliable operation of crystals with widely varying fundamental modes of oscillation. In accordance with exemplary embodiments, an architecture is disclosed for an oscillator circuit which allows reliable operation for crystals varying over a wide frequency range, such as 12:1. Some embodiments use selectable current sources to provide variable range control for extending the range of frequencies over which the embodiments may operate properly. Other embodiments include symmetric topologies, cascode topologies, coupling elements, and/or other techniques to improve noise immunity and/or operation in low-source-voltage environments.

Abstract: A gain control system comprises a reference stage, a bias replication stage, an operational amplifier, an automatic gain control block, a gain stage, and a crystal oscillator in one embodiment. A negative feedback loop is formed by portions of the operational amplifier, the replica biasing stage, the gain stage, and the automatic gain control stage. The negative feedback loop operatively controls an amplitude of oscillation in the crystal oscillator. The automatic gain control block produces output currents at reference levels in proportion to an input current source. The output current reference levels provide a corresponding yet independent scaling of currents in the bias replication stage and the gain stage. By the scaling capabilities provided a high common mode of voltage is provided between the crystal oscillator and the voltage reference section while stable oscillating characteristics are provided over a broad frequency range.

Abstract: A power-on reset circuit produces a reset signal output configured by an upper trip-point in an input hysteresis characteristic of the circuit. The upper trip-point is configured by resistances of a first pair of resistors coupled in series at an internal voltage reference node. A temperature coefficient of the upper trip-point is configured by resistance values of a second pair of resistors where each resistor is coupled with a corresponding switching device with an associated switching threshold. A magnitude of the input hysteresis characteristic is configured by resistances of a third pair of resistors in series. The magnitude of hysteresis is configured independent of configuring either the level or the temperature coefficient of the upper trip-point.

Abstract: A buffer device coupled to at least one input/output port of an integrated circuit has a plurality of control inputs configured to receive configuration programming information. The at least one input/output circuit is capable of: (a) being configured in a directional sense of communication by the configuration programming information, (b) being configured as an input circuit which can be further configured to provide input logic switching level thresholds according to the configuration programming information, and (c) being configured as at least one output circuit which can be further configured to provide an output drive strength according to the configuration programming information.

Abstract: A voltage-controlled oscillator is implemented with a succession of delay cells coupled in series to form an oscillator loop. The oscillator loop is supplied with reference voltages produced by a voltage generator. The reference voltages produce stable operation of the voltage-controlled oscillator. Cascode reference current generators are incorporated within the voltage generator to supply a cross-coupled arrangement of pull-up devices within each delay cell. The cross-coupled pull-up devices are instrumental in producing complementary output signaling from each delay cell. A pair of cascode current generators is configured in parallel to produce a magnitude of current according to an applied voltage and be selectable for dual or single operation with a corresponding frequency determination.

Abstract: A programmable volatile memory cell has a reset device in communication with a bit store. The reset device may produce a high or low logic state within a latch loop when activated by an assertive logic level on a reset line. A set of mask programmable vias may be provided on a single mask layer in a semiconductor fabrication process for the memory cell. A program-selectable one of two sets of vias may communicate with one reset device to the reset line and the other reset device to ground. In this way a single and programmatically determinable logic state may be produced in the memory cell with reset signaling. Otherwise, the memory cell is capable of retaining a logic state according to read/write processes. The memory cell may be implemented in an array where all or some of the cells may be reset at once.