Abstract: A built-in self-test apparatus for a digital-to-analog converter uses a differentiation unit for differentiating a digital-to-analog (DA) signal to obtain the differences between pulses of the analog signal. Next, the analog signal is converted into a digital signal in the light of a threshold voltage by a Schmitt trigger unit. Then, the duty cycles of the digital signal are calculated by a duty cycle retriever, and transmitted into a signature analyzer to calculate the differential non-linearity for error analysis. For processing a high-speed DA signal, the circuit disposed before the differentiation unit may use a test pattern unit, a sample-and-hold circuit and a logic circuit to lower the speed of the DA signal.

Abstract: The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and from left to right. Each square is provided with a first diagonal in ?45 degrees from the upper left to the lower right, and a second diagonal in +45 degrees from the lower left to the upper right. The present invention is to program the cells in the first diagonal or the second diagonal, and then read the cells except the first diagonal or the second diagonal; or, program the cells except the first diagonal or the second diagonal, and then read the cells in the first diagonal or the second diagonal so as to detect the disturb fault in the flash memories and normal memory fault models.

Abstract: A measuring method for signal jitter comprises the following procedures: First, a first data signal is provided, and the first data signal is deemed equivalent to a second data signal, wherein frequency of the first data signal is a multiple (preferably odd) of that of the second data signal, and at the same time, the ascent and the descent edges of the second data signal are the same as that of the first data signal. The widths of the high and low levels of the second data signal are counted so as to generate an estimated jitter stream including the estimated jitter values of the ascent and the descent edges of the second data signal. Then, jitter distribution diagrams of the ascent and the descent edges are established based on the estimated jitter stream, so as to calculate an eye open (EO) value.

Abstract: A constant current source with threshold voltage and channel length modulation comprises a set of cascade transistors and a compensation circuit electrically connected to the set of cascade transistors so as to form a feedback circuit, in which the set of cascade transistors including a first MOS transistor and a second MOS transistor, and the compensation circuit comprises a third MOS transistor, a fourth MOS transistor, a sixth MOS transistor and a seventh MOS transistor. The gate terminal of the third MOS transistor is connected to the gate terminal of the second MOS transistor. The fourth MOS transistor is connected to the third MOS transistor in serial, and the gate terminal of the fourth MOS transistor is connected to the gate terminal of the first MOS transistor, and the second terminal of the fourth MOS transistor is connected to a current-supplying circuit.

Abstract: A built-in-self-test apparatus for an analog-to-digital converter includes a digital-to-analog converter, a low-pass filter, a histogram analyzer and a software engine. The digital-to-analog converter is intended to generate a first signal. The low-pass filter is intended to smoothen the first signal so that an analog-to-digital converter can perform sampling on the smoothened first signal by a second signal, wherein the bit number of the second signal is greater than or equal to that of the first signal, and the frequency of the second signal is a multiple of that of the first signal. The histogram analyzer is electrically connected to the output end of the analog-to-digital converter. The software engine is electrically connected to the output end of the histogram analyzer so as to display the characteristics of the analog-to-digital converter.

Abstract: A constant current source with threshold voltage and channel length modulation includes first, second, third, fourth and fifth MOS transistors. Each of the MOS transistors has gate, first and second terminals. The first terminal of the second MOS transistor is coupled to loading impedance, and its second terminal is coupled with the first terminal of the first MOS transistor. The gate terminal and first terminal of the third MOS transistor are together coupled to the gate terminal of the second MOS transistor, and its second terminal is coupled to the first terminal of the fourth MOS transistor. The gate terminal and first terminal of the fourth MOS transistor are coupled to the gate terminal of the first MOS transistor, and its second terminal is coupled to a first reference voltage.