Abstract: The present disclosure is directed to a method of forming a conductive trace in a substrate. A pattern of the trace is formed in the substrate by a laser machining technique. The pattern of the trace is covered by palladium colloid. The palladium colloid is transferred to the patterned substrate by a laser-induced forward transfer (LIFT) technique. The palladium colloid is converted to a palladium plating catalyst layer by a palladium acceleration process. The palladium plating catalyst layer provides a sufficient catalyst to grow a metal seeding layer by an electroless copper deposition technique. In addition, the palladium plating catalyst layer includes portions of tin material which increases adhesion of the metal seeding layer into the substrate. After growing the metal seeding layer, the pattern of the trace is filled by a copper layer through an electrochemical deposition technique.

Abstract: One or more semiconductor dice are arranged on a die pad of a leadframe having an array of electrically conductive leads around the die pad. A pattern of electrically conductive wires is provided to couple the semiconductor die or dice with electrically conductive leads in the array around the die pad. An encapsulation of insulating material is provided to encapsulate the semiconductor die or dice arranged on the die pad and the pattern of electrically conductive wires.

Abstract: In an electronic device, a pulse generator receives an input signal and a clock signal and produces a transmission signal that includes a pulse following each edge of the input signal and of the clock signal. The pulse is low when the input signal is low and high when the input signal is high. A transmitter produces, at its two output nodes, a replica of the transmission signal and the complement of the transmission signal. A galvanic isolation barrier is coupled to the output nodes of the transmitter and produces a differential signal that includes a positive spike at each rising edge of the transmission signal and a negative spike at each falling edge of the transmission signal.

Abstract: A sensor device includes an infrared sensor configured to generate sensor data. The sensor device also includes a configurable digital analysis block. The configurable digital analysis block is configured to generate classification data based on the sensor data. The configurable digital analysis block includes a plurality of selectable analysis blocks that can be selectively included in generating the classification data.

Abstract: MEMS device comprising: a signal processing assembly; a transduction module comprising a plurality of transducer devices; a stiffening structure at least partially surrounding each transducer device; one or more coupling pillars for each transducer device, extending on the stiffening structure and configured to physically and electrically couple the transduction module to the signal processing assembly, to carry control signals of the transducer devices. Each conductive coupling element has a section having a shape such as to maximize the overlapping surface with the stiffening structure around the respective transducer device. This shape includes hypocycloid with a number of cusps equal to or greater than three; triangular; quadrangular.

Abstract: A microelectromechanical device includes: a support body; at least one movable mass of semiconductor material, elastically constrained to the support body so as to be able to oscillate; fixed detection electrodes rigidly connected to the support body and capacitively coupled to the at least one movable mass; and at least one test structure of semiconductor material, rigidly connected to the support body and distinct from the fixed detection electrodes. The test structure is capacitively coupled to the at least one movable mass and is configured to apply electrostatic forces to the at least one movable mass in response to a voltage between the test structure and the at least one movable mass.

Abstract: A body of semiconductor material has a surface and accommodates an active area, conductive regions, a first deep insulation structure extending in the active area from the surface of the body in a first trench, and a second deep insulation structure extending in the active area from the surface of the body in a second trench and surrounding the conductive regions. The first deep insulation structure has insulation walls surrounding a conductive filling portion. The second deep insulation structure has a solid insulating region filling the second trench. The first deep insulation region has a first width and a first depth and the second deep insulation structure has a second width and a second depth. The second width is smaller than the first width and the second depth is smaller than the first depth.

Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.

Abstract: A device includes a memory and processing circuitry coupled to the memory. The processing circuitry, in operation: estimates an angular rate of change and determines a rotational versor based on the rotational data; and estimates a gravity vector based on the angular rate of change and the rotational versor. The processing circuitry generates a dynamic gravity vector based on the estimated gravity vector, a correction factor and an estimated error in estimated gravity vector. The processing circuitry estimates a linear acceleration and determines an acceleration versor based on the acceleration data, and determines the correction factor based on the linear acceleration. The processing circuitry estimates the error in the estimated gravity vector based on the acceleration versor.

Abstract: An IMC circuit includes a memory cells arranged in matrix. Computational weights for an IMC operation are stored in groups of cells. Each row of groups of cells includes a positive and negative word linen. Each column of groups of cells includes a bit line. The IMC operation includes a first elaboration where a word line signal is applied to the positive/negative word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a positive MAC output on the bit line. In a second elaboration, a word line signal is applied to the negative/positive word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a negative MAC output on the bit line. The IMC operation result is obtained from a difference between the positive and negative MAC operations.

Abstract: Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.

Abstract: Electrically insulating material such as an epoxy resin is molded onto a sculptured, electrically conductive leadframe structure comprising a pattern of electrically conductive formations. The electrically insulating material penetrates into spaces between electrically conductive formations in the pattern of electrically conductive formations to provide a pre-molded leadframe structure configured to have at least one semiconductor die arranged thereon. The pre-molded leadframe structure has opposed first and second surfaces and a pre-molded leadframe thickness between the first surface and the second surface. The sculptured, electrically conductive leadframe structure comprises one or more connection formations connected with electrically conductive formations in the pattern of electrically conductive formations. The connection formation or formations have a first thickness equal to the thickness between the first surface and the second surface.

Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.

Abstract: A MEMS inclinometer includes a substrate, a first mobile mass and a sensing unit. The sensing unit includes a second mobile mass, a number of elastic elements, which are interposed between the second mobile mass and the substrate and are compliant in a direction parallel to a first axis, and a number of elastic structures, each of which is interposed between the first and second mobile masses and is compliant in a direction parallel to the first axis and to a second axis. The sensing unit further includes a fixed electrode that is fixed with respect to the substrate and a mobile electrode fixed with respect to the second mobile mass, which form a variable capacitor.

Abstract: A control circuit for an electronic converter is generates a drive signal of the electronic converter by setting the drive signal to a first logic level in response to a switch-on signal, and to a second logic level in response to a switch-off signal. The control circuit comprises a valley detection circuit and a combinational logic circuit. The control circuit comprises a blanking circuit configured to generate the blanking signal by determining a blanking time, and asserting the blanking signal when the blanking time elapses since the start of the switch-on or the switch-off interval. The control circuit comprises a blanking time adaption circuit to adapt the blanking time as a function of a blanking time adaption signal based on the input voltage, and to increase the blanking time when the input voltage increases, and decrease the blanking time when the input voltage decreases.

Abstract: A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.

Abstract: A method of managing an integrated circuit memory includes identifying a set of allocated regions and a set of empty regions spanning a memory space of an integrated circuit card, selecting the biggest empty region of the set of empty regions, determining that an allocated memory block of an allocated region immediately adjacent to the biggest empty region is larger than the biggest remaining empty region of the memory space, storing the allocated memory block in a temporary list of skipped memory blocks, removing the allocated memory block from the set of allocated memory regions, and swapping the allocated memory block with a remaining empty region to widen the biggest empty region.

Abstract: An integrated device includes: a semiconductor structural layer, including silicon carbide and having a first conductivity type; a power device integrated in the structural layer; and an edge termination structure, extending in a ring around the power device and having a second conductivity type. The edge termination structure includes a plurality of ring structures each arranged around the power device and in contiguous pairs. At least a first one of the ring structures comprises a transition region contiguous to a second one of the ring structures. The transition region includes connection regions, having the second conductivity type, connected to the second one of the ring structures and alternating with charge control regions having the first conductivity type.

Abstract: The present disclosure is directed to devices and methods for performing screen state detection. The screen state detection may be used in conjunction with any device with a bendable display. The device and method utilizes an electrostatic charge variation sensor to detect whether the display is in an open state or a closed state.

Abstract: A configurable voltage regulating circuit includes first through fourth switches. A flying capacitor is coupled between a common mode node and a pump node, and a sense resistance network is coupled between an output node and an input of an error amplifier and configured to provide a sensed output voltage. The error amplifier receives at another input a reference voltage and generates an error signal. A charging circuit supplies a charging current to the pump node, and controls the value of the charging current as a function of the error signal. A switch command signals generator generates respective first, second, third, and fourth switch signals to control the first switch, second switch, third switch, and fourth switch. The generator sets the configurable voltage regulating circuit as either a charge pump or a linear regulator based the input voltage being less than a first threshold or greater than a second threshold.