Abstract: A multiple-element modular package is provided which includes a plurality of level-one packages in horizontal or vertical stacked configuration.

Abstract: Thin and durable level-one and level-two integrated circuit packages are provided. A plurality of level-one integrated circuit packages may be aligned and securely bound in a stacked configuration by use of a flexible high temperature material, such as silicon adhesive tape or a conformal coating, to form a thin and durable horizontal level-two package, or stack. Various thermal conductors may be thermally coupled to the level-two package to help dissipate heat.

Abstract: The memory addressing system of the present invention incorporates industry standard features for compatibility and adds the capability of using high-density module memory boards exclusively or in combination with current or next generation standard memory modules without increasing system power requirements. The system provides a plurality of standardized memory module circuit board sockets that are electrically connected so as to provide address decoded RAS signals in addition to the standard row and column addressing signals.

Abstract: The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lower major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface. The result is an ultra-thin integrated circuit package that is thermally and mechanically balanced to prevent warping.

Abstract: The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lower major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface and after a layer of adhesive has been applied to the thin layer of material and cured.

Abstract: Thin and durable level-one and level-two integrated circuit packages are provided. A thin and durable level-one package is achieved in one method involving a molding technique of evenly applying molding compound to an integrated circuit die element. The casing surrounding a die element may be reduced or eliminated in part to thin the level-one package provided any necessary steps are taken to ensure the integrity of the package. Moisture-barriers, as an example, may be provided to the upper and/or lower surfaces of the thin level-one package. Additionally, a thin level-one package may also be constructed with one or more metal layers to prevent warpage. These level-one packages may be aligned in a stacked configuration to form a thin and durable horizontal level-two package. Various thermal conductors may be thermally coupled to the level-two package to help dissipate heat.

Abstract: An ultra-thin level-one integrated circuit package with improved moisture penetration characteristics manufactured using a transfer molded casing with metallic lamination layers is provided. Additionally, a method and apparatus for providing a multiple-element modular package including a plurality of such level-one packages in horizontal or vertical stack configuration is provided.

Abstract: A method and apparatus for tinning and soldering metal parts of electronic components and assemblies, and removing excess solder therefrom. The metal parts of the electronic components and assemblies are heated to a temperature near that of molten solder. A holding fixture, adapted to hold the heated components, slidably connects to an acceleration means which dips the metal parts of the components into the molten solder. Then acceleration energy is applied to the acceleration means, causing it to rapidly remove the components from the molten solder. Rapidly removing the components from the molten solder leaves excess solder behind, whereby all metal parts of the components are thoroughly tinned and soldered together without leaving unwanted solder bridges therebetween. A vibration means may also be used to prevent solder voids and promote solder wetting in densely packed leads and rails being tinned.

Abstract: A method and apparatus for achieving lead-on-chip integrated circuit packages by transferring at least one extremely thin adhesive from a carrier onto the face of integrated circuit chips, laminating a lead frame to the last adhesive layer, curing the adhesive to act as an insulator, bonding to the integrated circuit chip connection pads and encapsulating the chip and lead frame. A polypropylene carrier having adhesive patches pre-shaped and oriented in relation to the integrated circuit chips is brought into contact with the heated chips by either vacuum or pressure action wherein the adhesive is transferred from the polypropylene carrier to the faces of the chips. Thermally conductive and electrically insulating filling may be used with the adhesive to improve heat conduction from the IC. Compliant adhesive reduces thermally induced stresses between the lead frame and IC chip.