Abstract: A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first insulation layer, forming a second insulation layer over the first conductive layer, and forming a second conductive layer over the second insulation layer. A portion of the second insulation layer, first conductive layer, and second conductive layer form an integrated passive device (IPD). The IPD can be an inductor, capacitor, or resistor. A plurality of conductive pillars is formed over the second conductive layer. One conductive pillar removes heat from the semiconductor device. A third insulation layer is formed over the IPD and around the plurality of conductive pillars. A shield layer is formed over the IPD, third insulation layer, and conductive pillars. The shield layer is electrically connected to the conductive pillars to shield the IPD from electromagnetic interference.

Abstract: In a semiconductor device, a plurality of conductive pillars is formed over a temporary carrier. A dual-active sided semiconductor die is mounted over the carrier between the conductive pillars. The semiconductor die has first and second opposing active surfaces with first contact pads on the first active surface and second contact pads on the second active surface. An encapsulant is deposited over the semiconductor die and temporary carrier. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure is electrically connected to the conductive pillars and first contact pads of the dual-active sided semiconductor die. The temporary carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive pillars and second contact pads of the dual-active sided semiconductor die.

Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is disposed around the semiconductor die to form a peripheral area. An interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A plurality of vias is formed partially through the peripheral area of the encapsulant and offset from the semiconductor die. A portion of the encapsulant is disposed over a second surface of the semiconductor die opposite the first surface. The plurality of vias comprises a depth greater than a thickness of the portion of the encapsulant. A first portion of the plurality of vias is formed in a row offset from a side of the semiconductor die. A second portion of the plurality of vias is formed as an array of vias offset from a corner of the semiconductor die. A repair material disposed within the plurality of vias.

Abstract: A semiconductor device has a first conductive layer formed over a first substrate. A second conductive layer is formed over a second substrate. A first semiconductor die is mounted to the first substrate and electrically connected to the first conductive layer. A second semiconductor die is mounted to the second substrate and electrically connected to the second conductive layer. The first semiconductor die is mounted over the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and the first and second substrates. A conductive interconnect structure is formed through the encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device. Forming the conductive interconnect structure includes forming a plurality of conductive vias through the encapsulant and the first substrate outside a footprint of the first and second semiconductor die.

Abstract: A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier such that the sacrificial adhesive is disposed between the contact pads and temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and sacrificial adhesive is removed to leave a via over the contact pads. An interconnect structure is formed over the encapsulant. The interconnect structure includes a conductive layer which extends into the via for electrical connection to the contact pads. The semiconductor die is offset from the interconnect structure by a height of the sacrificial adhesive.

Abstract: An integrated circuit packaging system including: connecting a first integrated circuit device and a package substrate; attaching a support bump to the package substrate; providing a second integrated circuit device having an inner encapsulation; applying a magnetic film on the inner encapsulation of the second integrated circuit device; and mounting the second integrated circuit device over the first integrated circuit device with the magnetic film on the first integrated circuit device and the support bump.

Abstract: A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.

Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.

Abstract: A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points.

Abstract: A semiconductor device has a semiconductor die mounted to a substrate. A leadframe has a base plate and integrated tie bars and conductive bodies. The tie bars include a down step with an angled surface and horizontal surface between the conductive bodies. The leadframe is mounted to the semiconductor die and substrate with the base plate disposed on a back surface of the semiconductor die and the conductive bodies disposed around the semiconductor die and electrically connected to the substrate. An encapsulant is deposited over the substrate and semiconductor die and into the down step of the tie bars. A conductive layer is formed over the conductive bodies to inhibit oxidation. The leadframe is singulated through the encapsulant in the down step and through the horizontal portion of the tie bars to electrically isolate the conductive bodies. A semiconductor package can be mounted to the substrate and semiconductor die.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting platform; applying an attach layer on the mounting platform; mounting an integrated circuit die on the attach layer; forming an encapsulation on the integrated circuit die and the attach layer, the mounting platform exposed from the encapsulation; and forming a terminal having a terminal protrusion from the leadframe, the terminal protrusion below a horizontal plane of the mounting platform.

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: discrete components coupled to a top trace; vias attached to the top trace separated from the discrete components; a dielectric layer on the top trace, the discrete components, and the vias, includes a component surface formed above the discrete components, with the top trace coplanar with the dielectric layer; and system interconnects coupled to the vias for electrically connecting the top trace, the discrete components, or a combination thereof to the system interconnects.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion, the contact protrusion having a lower protrusion surface, an upper protrusion surface, and a protrusion sidewall; forming a die paddle, adjacent to the isolated contact, having a die paddle protrusion, the die paddle protrusion having a lower die protrusion surface, an upper die protrusion surface, and a die protrusion sidewall; depositing a contact pad on the contact protrusion; depositing a die paddle pad on the die paddle protrusion; coupling an integrated circuit die to the contact protrusion; and molding an encapsulation on the integrated circuit die.

Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A patterned trench is formed in the first insulating layer. A conductive ink is deposited in the patterned trench by disposing a stencil over the first insulating layer with an opening aligned with the patterned trench and depositing the conductive ink through the opening in the stencil into the patterned trench. Alternatively, the conductive ink is deposited by dispensing the conductive ink through a nozzle into the patterned trench. The conductive ink is cured by ultraviolet light at room temperature. A second insulating layer is formed over the first insulating layer and conductive ink. An interconnect structure is formed over the conductive ink. An encapsulant can be deposited around the semiconductor die. The patterned trench is formed in the encapsulant and the conductive ink is deposited in the patterned trench in the encapsulant.

Abstract: A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a component side and a system side; depositing a solder resist layer on the component side of the package substrate; patterning groups of access openings and a die mount opening in the solder resist layer; attaching an integrated circuit die in the die mount opening; forming conductive contacts in the access openings; and attaching system interconnects to the system side of the package substrate including controlling a coplanarity of the system interconnects by the solder resist layer.

Abstract: An integrated circuit packaging system and method of manufacture thereof including: a base substrate; an integrated circuit die on the base substrate; vertical interconnects attached to the base substrate around the integrated circuit die; and a single metal layer interposer mounted on the vertical interconnects, the single metal layer interposer including: a routing pattern having interposer contacts and traces, and a dielectric layer on the interposer contacts and traces, a top surface of the interposer contacts coplanar with a top surface of the dielectric layer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace.

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.