Abstract: A network interface for a first network on chip resource capable of interfacing a data processing unit in the first resource with the network, the network interface including an output communication controller including a mechanism detecting an indicator marking an end of communication between the first resource and at least one second resource with which a communication link is set up, and a mechanism outputting a signal indicating closure of the link to be sent to the second resource, after detection of an end of communication indicator.

Abstract: A system for performing depth-based scaling of 3D content. The system comprises: 1) a content source configured to provide an input image comprising a plurality of input image objects; and 2) a processor configured to receive the input image and to receive a depth map comprising depth data associated with each of the plurality of input image objects. The processor generates an output image comprising a plurality of output image objects, wherein each of the plurality of output image objects corresponding to one of the plurality of input image objects. The processor scales a size of a first output image object relative to the size of a second output image object based on depth data associated with the first output image object and the second output image object.

Abstract: Interference cancellation for wideband and narrowband communications systems is provided without apriori knowledge of statistical information about an interfering signal. In one embodiment a demodulator circuit can operate in an environment where a “no lock” situation would normally occur to remove the interference and acquire signals in low signal-to-noise ratio conditions and high signal-to-interference ration conditions. In other embodiments, performance is improved by introducing statistics of the interfering signal, and these statistics regarding the communications channel and interference properties (i.e., characteristics of the interfering signal) can be adaptive or “learned” in other embodiments.

Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.

Abstract: A network interface for a first network on chip resource capable of interfacing a data processing unit in the first resource with the network, the network interface including an output communication controller including a mechanism detecting an indicator marking an end of communication between the first resource and at least one second resource with which a communication link is set up, and a mechanism outputting a signal indicating closure of the link to be sent to the second resource, after detection of an end of communication indicator.

Abstract: A system and method for adjusting the perceived depth of stereoscopic images are provided. The system includes a disparity estimator, a disparity processor and a warping engine. The disparity estimator is configured to receive a stereoscopic image, to estimate disparities in the stereoscopic image, and to generate an estimator signal comprising the estimated disparities. The disparity processor is configured to receive the estimator signal from the disparity estimator and a depth control signal that is generated based on a user input. The disparity processor is also configured to generate a processor signal based on the estimator signal and the depth control signal. The warping engine is configured to receive the processor signal and to generate an adjusted stereoscopic image by warping the processor signal based on a model.

Abstract: A system for adjusting the perceived depth of 3D content in response to a viewer input control signal. The system comprises: 1) a content source providing an input left stereoscopic image and an input right stereoscopic image; 2) a disparity estimator to receive the input left and right stereoscopic images, detect disparities between the input left and right stereoscopic images, and generate a disparities array; and 3) processing circuitry to fill in occlusion areas associated with the disparities array and apply a scale factor to the detected disparities to thereby generate a scaled disparities array. The system further comprises a warping engine to receive the scaled disparities array and generate an output left stereoscopic image and an output right stereoscopic image. The output left and right stereoscopic images have a different perceived depth than the input left and right stereoscopic images.

Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.

Abstract: A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.

Abstract: Display 105 is capable of rendering, or otherwise displaying, one or more of a standard definition (SD) image, a two-dimensional (2D), a three-dimensional image (3D) and a high definition (HD) image 110.

Abstract: A fractional rate LC VCO and compensating divider circuit to avoid bit-rate interference includes an LC PLL having an input for receiving a reference clock signal, an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal, a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL, a second divider circuit having an input coupled to the output of the LC PLL, and an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO.

Abstract: A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.

Abstract: An image processing system includes an image reconstruction unit. The image reconstruction unit is configured to receive an image at a first resolution, apply the image to a look-up table and output a version of the image at a second resolution. The second resolution includes a higher resolution than the first resolution. In addition, the look-up table is generated inputting a plurality of training images; classifying, into a number of classes, a plurality of images patches corresponding to each of the plurality of training images; re-classifying the number of classes into a final class; and synthesizing filters corresponding to each of the class into a final filter value.

Abstract: A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.

Abstract: A system for performing depth-based scaling of 3D content. The system comprises: 1) a content source configured to provide an input image comprising a plurality of input image objects; and 2) a processor configured to receive the input image and to receive a depth map comprising depth data associated with each of the plurality of input image objects. The processor generates an output image comprising a plurality of output image objects, wherein each of the plurality of output image objects corresponding to one of the plurality of input image objects. The processor scales a size of a first output image object relative to the size of a second output image object based on depth data associated with the first output image object and the second output image object.

Abstract: A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.

Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plu

Abstract: Display 105 is capable of rendering, or otherwise displaying, one or more of a standard definition (SD) image, a two-dimensional (2D), a three-dimensional image (3D) and a high definition (HD) image 110

Abstract: A system and method for adjusting the perceived depth of stereoscopic images are provided. The system includes a disparity estimator, a disparity processor and a warping engine. The disparity estimator is configured to receive a stereoscopic image, to estimate disparities in the stereoscopic image, and to generate an estimator signal comprising the estimated disparities. The disparity processor is configured to receive the estimator signal from the disparity estimator and a depth control signal that is generated based on a user input. The disparity processor is also configured to generate a processor signal based on the estimator signal and the depth control signal. The warping engine is configured to receive the processor signal and to generate an adjusted stereoscopic image by warping the processor signal based on a model.

Abstract: An image processing system includes an image reconstruction unit. The image reconstruction unit is configured to receive an image at a first resolution, apply the image to a look-up table and output a version of the image at a second resolution. The second resolution includes a higher resolution than the first resolution. In addition, the look-up table is generated inputting a plurality of training images; classifying, into a number of classes, a plurality of images patches corresponding to each of the plurality of training images; re-classifying the number of classes into a final class; and synthesizing filters corresponding to each of the class into a final filter value.