Patents Assigned to STMicroelectronics (Crolle 2) SAS
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Publication number: 20240186090Abstract: The present description concerns a switch based on a phase-change material comprising: first, second, and third electrodes; a first region of said phase-change material coupling the first and second electrodes; and —a second region of said phase-change material coupling the second and third electrodes.Type: ApplicationFiled: March 30, 2023Publication date: June 6, 2024Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Philippe CATHELIN, Frederic GIANESELLO, Alain FLEURY, Stephane MONFRAY, Bruno REIG, Vincent PUYAL
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Publication number: 20240183745Abstract: A device for testing an optical device, comprising a first structure comprising a substrate made of a first material and at least two first pillars of cylindrical shape made of a second material crossing the substrate, the second material having an optical index different from the optical index of the first material.Type: ApplicationFiled: November 29, 2023Publication date: June 6, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Stephanie AUDRAN, Elodie SUNGAUER, Simon GUILLAUMET
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Patent number: 12004432Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.Type: GrantFiled: October 21, 2021Date of Patent: June 4, 2024Assignees: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe Boivin, Roberto Simola, Yohann Moustapha-Rabault
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Publication number: 20240176129Abstract: The present description concerns an optical filter intended to be arranged in front of an image sensor comprising a plurality of pixels, the filter comprising, for each pixel, at least one resonant cavity comprising a transparent region having a first refraction index and laterally delimited by a reflective peripheral vertical wall, and at least one resonant element formed in said region.Type: ApplicationFiled: March 30, 2023Publication date: May 30, 2024Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SASInventors: Sandrine VILLENAVE, Quentin ABADIE
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Publication number: 20240178055Abstract: The present description concerns a method of manufacturing an insulating trench in a substrate, for an electronic device, comprising the following successive steps: (a) filling a trench formed in the substrate with a first insulating material; (b) depositing a first etch stop layer on the first material; (c) depositing a second layer of a second insulating material on the first etch stop layer; (d) etching down to the etch stop layer; and (e) depositing a third layer made of a third tight material.Type: ApplicationFiled: November 14, 2023Publication date: May 30, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Thierno Moussa BAH, Pascal GOURAUD, Patrick GROS D'AILLON, Emilie PREVOST
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Publication number: 20240178869Abstract: A reception element receives an analog signal. The received analog signal is converted by a reception chain into a digital signal. Based on the digital signal and a first filtering operation, a correction chain generates a correction digital signal reconstituting dynamic nonlinearities generated by the reception chain. A corrected signal from which the reconstituted dynamic nonlinearities have been removed is then generated by subtracting the correction digital signal from the digital signal.Type: ApplicationFiled: November 28, 2023Publication date: May 30, 2024Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, Centre National De La Recherche Scientifique, Universite Du MansInventors: Clement BONNAFOUX, Paul SVENSSON, Pascal URARD, Kosai RAOOF, Youssef SERRESTOU
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Patent number: 11994424Abstract: In an embodiment a method for measuring ambient light includes successively synchronizing optical signal acquisition phases with extinction phases of a disruptive light source, wherein the disruptive light source periodically provides illumination phases and the extinction phases, accumulating, in each acquisition phase, photo-generated charges by at least one photosensitive pixel comprising a pinned photodiode, wherein an area of the pinned photodiode is less than or equal to 1/10 of an area of the at least one photosensitive pixel, transferring, for each pixel, the accumulated photo-generated charges to a sensing node, converting, for each pixel, the transferred charges to a voltage at a voltage node and converting, for each pixel, the transferred charges to a digital number.Type: GrantFiled: January 5, 2022Date of Patent: May 28, 2024Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited, STMicroelectronics (Grenoble 2) SASInventors: Pierre Malinge, Frédéric Lalanne, Jeffrey M. Raynor, Nicolas Moeneclaey
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Patent number: 11996465Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.Type: GrantFiled: September 27, 2021Date of Patent: May 28, 2024Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Alexis Gauthier, Pascal Chevalier
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Publication number: 20240170586Abstract: The present disclosure concerns a photodiode including at least one memory area, each memory area including at least two charge storage regions.Type: ApplicationFiled: January 29, 2024Publication date: May 23, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Arnaud TOURNIER, Boris RODRIGUES GONCALVES, Frederic LALANNE, Pascal FONTENEAU
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Publication number: 20240162329Abstract: An electronic device includes an insulating first layer covering a second layer made of a doped semiconductor material. A cavity is formed to cross through the first layer and reach the second layer. Insulating spacers are forming against lateral walls of the cavity. A first doped semiconductor region fills the cavity. The first doped semiconductor region has a doping concentration decreasing from the second layer.Type: ApplicationFiled: November 6, 2023Publication date: May 16, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Alexis GAUTHIER, Pascal CHEVALIER, Edoardo BREZZA, Nicolas GUITARD
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Publication number: 20240162328Abstract: A bipolar transistor is manufactured by: forming a collector region; forming a first layer made of a material of a base region and an insulating second layer; forming a cavity reaching the collector region; forming a portion of the collector region and a portion of the base region in the cavity; forming an insulating fourth layer made of a same material as the insulating second layer in the periphery of the bottom of the cavity, the insulating fourth layer having a same thickness as the insulating second layer; forming an emitter region; and simultaneously removing the insulating second and a portion of the insulating fourth layer not covered by the emitter region.Type: ApplicationFiled: November 7, 2023Publication date: May 16, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Alexis GAUTHIER, Pascal CHEVALIER, Edoardo BREZZA, Nicolas GUITARD, Gregory AVENIER
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Publication number: 20240162186Abstract: A first wafer includes a first semiconductor layer and first metal contacts on a side of a first surface of the first semiconductor layer. A second wafer includes a second semiconductor layer and second metal contacts on a side of a first surface of the second semiconductor layer. A handle is bonded onto a surface of the second wafer opposite to the second semiconductor layer. The second semiconductor layer is then removed to expose the second metal contacts. A bonding is then performed between the first and second wafers to electrically connect the first metal contacts to the second metal contacts.Type: ApplicationFiled: November 13, 2023Publication date: May 16, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Sandrine LHOSTIS, Emilie DELOFFRE, Sebastien MERMOZ
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Patent number: 11984360Abstract: A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.Type: GrantFiled: April 25, 2022Date of Patent: May 14, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Gregory Avenier, Alexis Gauthier, Pascal Chevalier
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Publication number: 20240153557Abstract: A method for operating a sense amplifier in a one-switch one-resistance (1S1R) memory array, includes: generating a regulated full voltage and a regulated half voltage; applying the regulated full voltage and regulated half voltage to selected and unselected bit lines of the 1S1R memory array during read operations as an applied read voltage; and inducing and compensating for a sneak-path current during read operations by adjusting the applied read voltage based on the cell state of an accessed bit cell and an amplitude of the sneak-path current.Type: ApplicationFiled: December 11, 2023Publication date: May 9, 2024Applicants: Universite D'Aix Marseille, Centre National de la Recherche, STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Roussel) SASInventors: Jean-Michel PORTAL, Vincenzo DELLA MARCA, Jean-Pierre WALDER, Julien GASQUEZ, Philippe BOIVIN
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Patent number: 11978710Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.Type: GrantFiled: June 28, 2021Date of Patent: May 7, 2024Assignee: STMicroelectronics (Crolles 2) SASInventor: Didier Dutartre
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Patent number: 11978756Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.Type: GrantFiled: December 21, 2020Date of Patent: May 7, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Sonarith Chhun
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Publication number: 20240142806Abstract: A device includes a first pixel, based on quantum dots, configured to deliver event-based data for generating an event-based image, and second pixels, each second pixel based on quantum dots, configured to deliver light intensity data for generating a light intensity image.Type: ApplicationFiled: October 24, 2023Publication date: May 2, 2024Applicant: STMicroelectronics (Crolles 2) SASInventor: Arthur ARNAUD
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Publication number: 20240147737Abstract: A method of manufacturing an electronic chip includes the following successive steps: a) forming of a first layer on top of and in contact with a second semiconductor layer, the second layer being on top of and in contact with a third semiconductor layer; b) doping of the first layer to form, on the second layer, a first doped sub-layer of the first conductivity type and a second doped sub-layer of the second conductivity type; c) forming of islands in the first layer organized in an array of rows and of columns at the surface of the second layer; and d) forming of memory cells based on a phase-change material on the islands of the first layer.Type: ApplicationFiled: October 20, 2023Publication date: May 2, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Olivier WEBER, Remy BERTHELON
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Publication number: 20240125992Abstract: The present description concerns an optical filter intended to be arranged in front of an image sensor comprising a plurality of pixels, the filter comprising, for each pixel, a resonant cavity comprising a first transparent layer, interposed between second and third mirror layers, and a diffraction grating formed in the first layer, wherein at least one of the cavities has a different thickness than another cavity.Type: ApplicationFiled: March 28, 2023Publication date: April 18, 2024Applicants: STMicroelectronics (Crolles 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Quentin ABADIE, Sandrine VILLENAVE
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Publication number: 20240128289Abstract: The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.Type: ApplicationFiled: December 20, 2023Publication date: April 18, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Francois ROY, Andrej SULER