Patents Assigned to STMicroelectronics Crolles 2 SAS
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Publication number: 20240153557Abstract: A method for operating a sense amplifier in a one-switch one-resistance (1S1R) memory array, includes: generating a regulated full voltage and a regulated half voltage; applying the regulated full voltage and regulated half voltage to selected and unselected bit lines of the 1S1R memory array during read operations as an applied read voltage; and inducing and compensating for a sneak-path current during read operations by adjusting the applied read voltage based on the cell state of an accessed bit cell and an amplitude of the sneak-path current.Type: ApplicationFiled: December 11, 2023Publication date: May 9, 2024Applicants: Universite D'Aix Marseille, Centre National de la Recherche, STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Roussel) SASInventors: Jean-Michel PORTAL, Vincenzo DELLA MARCA, Jean-Pierre WALDER, Julien GASQUEZ, Philippe BOIVIN
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Patent number: 11978710Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.Type: GrantFiled: June 28, 2021Date of Patent: May 7, 2024Assignee: STMicroelectronics (Crolles 2) SASInventor: Didier Dutartre
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Patent number: 11978756Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.Type: GrantFiled: December 21, 2020Date of Patent: May 7, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Sonarith Chhun
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Publication number: 20240142806Abstract: A device includes a first pixel, based on quantum dots, configured to deliver event-based data for generating an event-based image, and second pixels, each second pixel based on quantum dots, configured to deliver light intensity data for generating a light intensity image.Type: ApplicationFiled: October 24, 2023Publication date: May 2, 2024Applicant: STMicroelectronics (Crolles 2) SASInventor: Arthur ARNAUD
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Publication number: 20240147737Abstract: A method of manufacturing an electronic chip includes the following successive steps: a) forming of a first layer on top of and in contact with a second semiconductor layer, the second layer being on top of and in contact with a third semiconductor layer; b) doping of the first layer to form, on the second layer, a first doped sub-layer of the first conductivity type and a second doped sub-layer of the second conductivity type; c) forming of islands in the first layer organized in an array of rows and of columns at the surface of the second layer; and d) forming of memory cells based on a phase-change material on the islands of the first layer.Type: ApplicationFiled: October 20, 2023Publication date: May 2, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Olivier WEBER, Remy BERTHELON
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Publication number: 20240125992Abstract: The present description concerns an optical filter intended to be arranged in front of an image sensor comprising a plurality of pixels, the filter comprising, for each pixel, a resonant cavity comprising a first transparent layer, interposed between second and third mirror layers, and a diffraction grating formed in the first layer, wherein at least one of the cavities has a different thickness than another cavity.Type: ApplicationFiled: March 28, 2023Publication date: April 18, 2024Applicants: STMicroelectronics (Crolles 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Quentin ABADIE, Sandrine VILLENAVE
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Publication number: 20240128289Abstract: The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.Type: ApplicationFiled: December 20, 2023Publication date: April 18, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Francois ROY, Andrej SULER
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Patent number: 11961868Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.Type: GrantFiled: May 17, 2023Date of Patent: April 16, 2024Assignee: STMicroelectronics (Crolles 2) SASInventor: Francois Roy
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Patent number: 11957067Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.Type: GrantFiled: May 24, 2021Date of Patent: April 9, 2024Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe Boivin, Simon Jeannot
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Patent number: 11955481Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.Type: GrantFiled: November 22, 2022Date of Patent: April 9, 2024Assignee: STMicroelectronics (Crolles 2) SASInventor: Jean Jimenez Martinez
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Patent number: 11947202Abstract: The present disclosure relates to a method including the following steps: a) forming a waveguide from a first material, the waveguide being configured to guide an optical signal; b) forming a layer made of a second material that is electrically conductive and transparent to a wavelength of the optical signal, steps a) and b) being implemented such that the layer made of the second material is in contact with at least one of the faces of the waveguide, or is separated from the at least one of the faces by a distance of less than half, preferably less than a quarter, of the wavelength of the optical signal. The application further relates to a phase modulator, in particular obtained by such a method.Type: GrantFiled: April 3, 2023Date of Patent: April 2, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Sébastien Cremer, Frédéric Boeuf, Stephane Monfray
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Integrated circuit comprising a single photon avalanche diode and corresponding manufacturing method
Patent number: 11949035Abstract: A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.Type: GrantFiled: December 9, 2021Date of Patent: April 2, 2024Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Denis Rideau, Dominique Golanski, Alexandre Lopez, Gabriel Mugny -
Patent number: 11948950Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.Type: GrantFiled: April 7, 2021Date of Patent: April 2, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Mickael Fourel, Laurent-Luc Chapelon
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Publication number: 20240105730Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.Type: ApplicationFiled: December 7, 2023Publication date: March 28, 2024Applicants: STMicroelectronics France, STMicroelectronics (Crolles 2) SASInventors: Olivier WEBER, Christophe LECOCQ
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Publication number: 20240096898Abstract: The present description concerns an electronic device comprising: a silicon layer, an insulating layer in contact with a first surface of the silicon layer, a transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the device further comprising, under the gate portion, a partial insulating trench in the silicon layer extending from a second surface of the silicon layer down to a depth smaller than the thickness of the silicon layer.Type: ApplicationFiled: March 27, 2023Publication date: March 21, 2024Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SASInventors: Tadeu MOTA FRUTUOSO, Xavier GARROS, Blandine DURIEZ, Sebastien CREMER
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Publication number: 20240097030Abstract: The present description concerns an electronic device comprising: —a silicon layer having a first surface and a second surface, —an insulating layer in contact with the first surface of the silicon layer, —at least one transistor comprising source, drain, and body regions arranged in the silicon layer, and a gate region topping the body region and comprising a gate portion laterally extending beyond the source and drain regions, the body region being continued by a body contact region not covered with the gate region, and a region of extension of the body region being located under the gate portion; the gate portion being less heavily doped than the rest of the gate region.Type: ApplicationFiled: March 27, 2023Publication date: March 21, 2024Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SASInventors: Sebastien CREMER, Tadeu MOTA FRUTUOSO, Xavier GARROS, Blandine DURIEZ
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Publication number: 20240081160Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Applicants: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe BOIVIN, Simon JEANNOT
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Publication number: 20240079421Abstract: The present description concerns an image sensor formed inside and on top of a semiconductor substrate, the sensor comprising a plurality of pixels, each comprising a photodetector formed in the substrate, the sensor comprising at least first and second bidimensional metasurfaces stacked, in this order, in front of said plurality of pixels, each metasurface being formed of a bidimensional array of pads, the first metasurface having a first optical function and the second metasurface having a second optical function different from the first optical function.Type: ApplicationFiled: March 17, 2023Publication date: March 7, 2024Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SASInventors: Axel CROCHERIE, Alain OSTROVSKY, Jerome VAILLANT, Francois DENEUVILLE
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Patent number: 11923465Abstract: The present disclosure concerns a photodiode including at least one memory area, each memory area including at least two charge storage regions.Type: GrantFiled: December 17, 2020Date of Patent: March 5, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Arnaud Tournier, Boris Rodrigues Goncalves, Frederic Lalanne
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Publication number: 20240063290Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.Type: ApplicationFiled: October 26, 2023Publication date: February 22, 2024Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Alexis GAUTHIER, Pascal CHEVALIER