Patents Assigned to STMicroelectronics Crolles SAS
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Publication number: 20240154034Abstract: A transistor includes a source region, a drain region and a body region arranged in a semiconductor layer. A gate region tops the body region. The body region includes a first doped layer and a second layer between the first doped layer and the gate region. The second layer is an epitaxial layer that is less heavily doped than the first doped layer.Type: ApplicationFiled: November 1, 2023Publication date: May 9, 2024Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Julien DURA, Franck JULIEN, Julien AMOUROUX, Stephane MONFRAY
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Patent number: 11031433Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.Type: GrantFiled: February 8, 2019Date of Patent: June 8, 2021Assignee: STMicroelectronics (Crolles) SASInventors: Frederic Lalanne, Laurent Gay, Pascal Fonteneau, Yann Henrion, Francois Guyader
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Patent number: 8492958Abstract: A device for converting thermal power into electric power including a plurality of bimetallic strips disposed between a rigid support and a plate of a resilient plastic material; and on the side of the plate of a resilient plastic material opposite to the strips, a layer of a piezoelectric material connected to output terminals, wherein the rigid support is capable of being in contact with a hot source, and the plate of a resilient plastic material is capable of transmitting to the piezoelectric layer the mechanical stress due to the deformations of the bimetallic strips.Type: GrantFiled: October 25, 2010Date of Patent: July 23, 2013Assignee: STMicroelectronics (Crolles) SASInventor: Thomas Skotnicki
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Patent number: 8378558Abstract: A thermoelectric generator including, between first and second walls delimiting a tightly closed space, a layer of a piezoelectric material connected to output terminals; a plurality of openings crossing the piezoelectric layer and emerging into first and second cavities close to the first and second walls; and in the tight space, drops of a liquid, the first wall being capable of being in contact with a hot source having a temperature greater than the evaporation temperature of the liquid and the second wall being capable of being in contact with a cold source having a temperature smaller than the evaporation temperature of the liquid.Type: GrantFiled: October 25, 2010Date of Patent: February 19, 2013Assignee: STMicroelectronics (Crolles) SASInventor: Thomas Skotnicki
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Patent number: 7749817Abstract: A system and method for producing a single-crystal germanium layer on a dielectric layer by producing a germanium-on-insulator assembly between the surface portions of the third material. The choice of location for these surface portions therefore makes it possible to define the zone on which it is desired to produce the germanium-on-insulator layer. The wafer may be freely chosen between a pure single-crystal silicon wafer and a silicon-on-insulator wafer. A single-crystal germanium first layer is produced on the surface portion of the silicon. The RPCVD produces a partially crystalline germanium first layer. The layer thus comprises various nuclei that have crystallized in possibly different lattices. After carrying out a recrystallization annealing operation, which makes the layer monocrystalline by recrystallizing the various nuclei in one and the same crystal lattice. Thus, the layers are continuous with the single-crystal silicon lattice.Type: GrantFiled: January 16, 2007Date of Patent: July 6, 2010Assignee: STMicroelectronics (Crolles) SASInventors: Olivier Kermarec, Yves Campidelli
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Publication number: 20100059834Abstract: An integrated electronic circuit has a thin layer portion based on hafnium oxide. This portion additionally contains magnesium atoms, so that the portion is in the form of a hafnium-and-magnesium mixed oxide. Such a portion has a high dielectric constant and a very low leakage current. It is particularly suitable for forming a part of a gate insulation layer of a MOS transistor or a part of a MIM capacitor dielectric.Type: ApplicationFiled: April 25, 2008Publication date: March 11, 2010Applicants: STMicroelectronics (Crolles) SAS, Centre National de La Recherche Scientifique - CNRS -, Institut National Polytechnique De GrenobleInventors: Catherine Dubourdieu, Erwan Yann Ruawel, Vincent Cosnier, Sandrine Lhostis, Daniel-Camille Bensahel
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Patent number: 7541636Abstract: A memory cell with one transistor on a floating body region isolated by its lower surface by a junction. According to the present invention, the junction is non-planar and, for example, includes a protrusion directed towards the transistor surface.Type: GrantFiled: June 30, 2006Date of Patent: June 2, 2009Assignee: STMicroelectronics Crolles SASInventors: Rossella Ranica, Alexandre Villaret, Pascale Mazoyer