Patents Assigned to STMicroelectronics, Inc.
  • Publication number: 20240145480
    Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.
    Type: Application
    Filed: May 31, 2023
    Publication date: May 2, 2024
    Applicant: STMICROELECTRONICS, INC.
    Inventor: John H. ZHANG
  • Patent number: 11968602
    Abstract: In an embodiment, a device comprises a memory, which, in operation, stores data samples associated with a plurality of data sensors, and circuitry, coupled to the memory, wherein the circuitry, in operation, generates synchronized output data sets associated with the plurality of data sensors. Generating a synchronized output data set includes: determining a reference sample associated with a sensor of the plurality of sensors; verifying a timing validity of a data sample associated with another sensor of the plurality of sensors; identifying a closest-in-time data sample associated with the another sensor of the plurality of sensors with respect to the reference sample; and generating the synchronized output data set based on interpolation.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: April 23, 2024
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS, INC.
    Inventors: Karimuddin Sayed, Chandandeep Singh Pabla, Lorenzo Bracco, Federico Rizzardini
  • Publication number: 20240124300
    Abstract: A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Applicant: STMicroelectronics, Inc.
    Inventor: Jefferson Sismundo TALLEDO
  • Publication number: 20240113064
    Abstract: An electronic device includes an integrated circuit (IC) with its second face bonded to a first surface of a first support. A conductive clip has a first portion that is elongate and extends across the IC, having its second surface bonded to a first face of the IC by a solder layer. A second portion of the clip extends from the first portion away from the IC toward a second support with the second surface bonded to a first surface of the second support. A first surface of the clip has a pattern formed therein including a depressed floor with fins extending upwardly therefrom. Through-holes extend through the depressed floor to the second surface of the clip. An encapsulating layer covers portions of the first and second supports, IC, and clip while leaving the first surface of the first portion exposed to permit heat to radiate away therefrom.
    Type: Application
    Filed: August 11, 2023
    Publication date: April 4, 2024
    Applicant: STMicroelectronics, Inc.
    Inventor: Jefferson Sismundo TALLEDO
  • Patent number: 11948977
    Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: April 2, 2024
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 11948868
    Abstract: Generally described, one or more embodiments are directed to a leadframe package having a plurality of leads, a die pad, a semiconductor die coupled to the die pad, and encapsulation material. An inner portion of the die pad includes a perimeter portion that includes a plurality of protrusions that are spaced apart from each other. The protrusions aid in locking the die pad in the encapsulation material. The plurality of leads includes upper portions and base portions. The base portion of the plurality of leads are offset (or staggered) relative to the plurality of protrusions of the die pad. In particular, the base portions extend longitudinally toward the die pad and are located between respective protrusions. The upper portions of the leads include lead locks that extend beyond the base portions in a direction of adjacent leads. The lead locks and the protrusion in the die pad aid in locking the leads and the die pad in the encapsulation material.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: April 2, 2024
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 11927443
    Abstract: A microelectromechanical device is provided. A vibrating structure gyroscope included in the device employs a temporal differential sensing method alone or a spatial differential sensing method in combination with the temporal differential sensing method. When used in combination, the temporal sensing method may be applied before the spatial sensing method or applied after the spatial sensing method. The temporal differential sensing samples signals at times t1 and t2 when velocity of a sensing mass within the vibrating structure gyroscope is maximum and has an opposite sign. The temporal sensing method improves Euler and Centrifugal forces cancellation and increases the signal to noise ratio if forces remain equal at times t1 and t2. Applying a high sampling speed can result in times t1 and t2 being sufficiently close to each other and therefore cancel any error terms associated with Euler and Centrifugal forces.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: March 12, 2024
    Assignee: STMicroelectronics, Inc.
    Inventor: Andrea Lorenzo Vitali
  • Patent number: 11929259
    Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: March 12, 2024
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Ian Harvey Arellano, Aaron Cadag, Ela Mia Cadag
  • Patent number: 11921655
    Abstract: A microcontroller includes a memory, direct memory access (DMA) controllers and a microprocessor. The microprocessor maintains one or more memory protection (MP) configurations to control access to protected memory areas of the microcontroller. In response to a secure service call of an unsecure user-application, the microprocessor executes a state machine which disables interrupt requests, determining whether DMA controller configurations and MP configurations satisfy secure-service criteria. When the secure-service criteria are satisfied, at least one secure operation associated with the secure service call is performed, and memory areas accessed during the execution of the at least one secure operation are cleaned. The interrupt requests are re-enabled and a response to the secure service call is generated.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: March 5, 2024
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Massimo Panzica, Maurizio Gentili
  • Publication number: 20240067184
    Abstract: A system includes inertial sensors and a GPS. The system generates a first estimated vehicle velocity based on motion data and positioning data, generates a second estimated vehicle velocity based on the processed motion data and the first estimated vehicle velocity, and generates fused datasets indicative of position, velocity and attitude of a vehicle based on the processed motion data, the positioning data and the second estimated vehicle velocity. The generating the second estimated vehicle velocity includes: filtering the motion data, transforming the filtered motion data in a frequency domain based on the first estimated vehicle velocity, generating spectral power density signals, generating an estimated wheel angular frequency and an estimated wheel size based on the spectral power density signals, and generating the second estimated vehicle velocity as a function of the estimated wheel angular frequency and the estimated wheel size.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 29, 2024
    Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS, INC., STMicroelectronics (Grand Ouest) SAS
    Inventors: Nicola Matteo PALELLA, Leonardo COLOMBO, Andrea DONADEL, Roberto MURA, Mahaveer JAIN, Joelle PHILIPPE
  • Patent number: 11916090
    Abstract: A first side of a tapeless leadframe package is etched to form a ring shaped protrusion and a lead protrusion extending from a base layer. An integrated circuit die is mounted to tapeless leadframe package in flip chip orientation with a front side facing the first side. An electrical and mechanical attachment is made between a bonding pad of the integrated circuit die and the lead protrusion. A mechanical attachment is made between the front side of the integrated circuit die and the ring shaped protrusion. The integrated circuit die and the protrusions from the tapeless leadframe package are encapsulated within an encapsulating block. The second side of the tapeless leadframe package is then etched to remove portions of the base layer and define a lead for a leadframe from the lead protrusion and further define a die support for the leadframe from the ring shaped protrusion.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: February 27, 2024
    Assignee: STMicroelectronics, Inc.
    Inventors: Aaron Cadag, Rohn Kenneth Serapio, Ela Mia Cadag
  • Patent number: 11897763
    Abstract: A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics, Inc.
    Inventor: Jefferson Sismundo Talledo
  • Publication number: 20240045001
    Abstract: An electronic device includes a magnetometer that outputs magnetometer sensor signals and a gyroscope that outputs gyroscope sensor signals. The electronic device includes a magnetometer calibration module that calibrates the magnetometer utilizing the gyroscope sensor signals. The electronic device generates a first magnetometer calibration parameter based on a Kalman filter process. The electronic device generates a second magnetometer calibration parameter based on a least squares estimation process.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Mahaveer JAIN, Mahesh CHOWDHARY
  • Publication number: 20240044646
    Abstract: A microelectromechanical device is provided. A vibrating structure gyroscope included in the device employs a temporal differential sensing method alone or a spatial differential sensing method in combination with the temporal differential sensing method. When used in combination, the temporal sensing method may be applied before the spatial sensing method or applied after the spatial sensing method. The temporal differential sensing samples signals at times t1 and t2 when velocity of a sensing mass within the vibrating structure gyroscope is maximum and has an opposite sign. The temporal sensing method improves Euler and Centrifugal forces cancellation and increases the signal to noise ratio if forces remain equal at times t1 and t2. Applying a high sampling speed can result in times t1 and t2 being sufficiently close to each other and therefore cancel any error terms associated with Euler and Centrifugal forces.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Applicant: STMICROELECTRONICS, INC.
    Inventor: Andrea Lorenzo VITALI
  • Patent number: 11862579
    Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: January 2, 2024
    Assignee: STMicroelectronics, Inc.
    Inventor: Ian Harvey Arellano
  • Publication number: 20230420390
    Abstract: A leadframe having extensions around an outer edge of a die pad are disclosed. More specifically, leadframes are created with a flange formed at the outer edge of the die pad and extending away from the die pad. The flange is bent, such that it is positioned at an angle with respect to the die pad. Leadframes are also created with anchoring posts formed adjacent the outer edge of the die pad and extending away from the die pad. The anchoring posts have a central thickness that is less than a thickness of first and second portions opposite the central portion. When the leadframe is incorporated into a package, molding compound completely surrounds each flange or anchoring post, which increases the bond strength between the leadframe and the molding compound due to increased contact area. The net result is a reduced possibility of delamination at edges of the die pad.
    Type: Application
    Filed: June 22, 2023
    Publication date: December 28, 2023
    Applicant: STMicroelectronics, Inc.
    Inventor: Jefferson Sismundo TALLEDO
  • Patent number: 11856657
    Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: December 26, 2023
    Assignees: STMICROELECTRONICS ASIA PACIFIC PTE LTD, STMICROELECTRONICS, INC.
    Inventors: Fuchao Wang, Olivier Leneel, Ravi Shankar
  • Publication number: 20230411251
    Abstract: The present disclosure is directed to a thin substrate package and a lead frame method of fabricating the semiconductor package. The semiconductor package includes a first lead frame portion and a second lead frame portion. A substrate is positioned in a center opening between the first lead frame portion and the second lead frame portion, the substrate having a thickness less than or equal to 0.10-millimeters (mm). A first die having a plurality of wires is positioned on the substrate by an adhesive. A molding compound covers the first and second lead frame portions, the substrate, and the first die.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 21, 2023
    Applicant: STMicroelectronics, Inc.
    Inventor: Jefferson Sismundo TALLEDO
  • Patent number: 11848256
    Abstract: Embodiments of the present disclosure are directed to leadframe semiconductor packages having die pads with cooling fins. In at least one embodiment, the leadframe semiconductor package includes leads and a semiconductor die (or chip) coupled to a die pad with cooling fins. The cooling fins are defined by recesses formed in the die pad. The recesses extend into the die pad at a bottom surface of the semiconductor package, such that the bottom surfaces of the cooling fins of the die pad are flush or coplanar with a surface of the package body, such as an encapsulation material. Furthermore, bottom surfaces of the cooling fins of the die pad are flush or coplanar with exposed bottom surfaces of the leads.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 19, 2023
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Jefferson Talledo
  • Patent number: 11834054
    Abstract: A system includes inertial sensors and a GPS. The system generates a first estimated vehicle velocity based on motion data and positioning data, generates a second estimated vehicle velocity based on the processed motion data and the first estimated vehicle velocity, and generates fused datasets indicative of position, velocity and attitude of a vehicle based on the processed motion data, the positioning data and the second estimated vehicle velocity. The generating the second estimated vehicle velocity includes: filtering the motion data, transforming the filtered motion data in a frequency domain based on the first estimated vehicle velocity, generating spectral power density signals, generating an estimated wheel angular frequency and an estimated wheel size based on the spectral power density signals, and generating the second estimated vehicle velocity as a function of the estimated wheel angular frequency and the estimated wheel size.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: December 5, 2023
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS, INC., STMicroelectronics (Grand Ouest) SAS
    Inventors: Nicola Matteo Palella, Leonardo Colombo, Andrea Donadel, Roberto Mura, Mahaveer Jain, Joƫlle Philippe