Abstract: In accordance with an embodiment, a reference voltage generator includes a first current generator and a second current generator. The first current generator is configured to produce a first current proportional to a current through a first diode connected in series with the first resistance coupled between a first voltage and a second voltage, such that the first current is produced according to a first proportionality constant. The second current generator is configured to produce a second current proportional to a current through a second diode connected in series with the second resistance coupled between the first voltage and the second voltage, such that the second current is produced according to a second proportionality constant. The reference voltage generator further includes a reference resistor coupled to the first and second current generators and to and output of the reference voltage generator.

Abstract: In accordance with an embodiment, a method of performing a successive approximation analog-to-digital (A/D) conversion includes determining a voltage range of an analog input voltage in a single cycle using a multi-bit flash A/D converter, determining an initial D/A value for a successive approximation based on determining the voltage range, and successively approximating the analog input voltage. Successively approximating includes providing the initial D/A value to a D/A converter, comparing an output of the D/A converter with the analog input voltage, and determining a further D/A value based on the comparing.

Abstract: An embodiment of a method is disclosed for encoding a digital video signal including a first video sequence and a second video sequence jointly forming a stereo-view digital video signal. The method includes: subjecting the first video sequence to discrete cosine transform, quantization and run-length coding to produce a sequence of blocks of non-zero digital levels representative of the first video sequence, subjecting the second video sequence to discrete cosine transform, quantization, run-length coding and variable length coding to produce digital messages representative of the second video sequence, merging the bits of the digital messages into the sequence of blocks of digital levels by substituting the bits of the digital messages for respective Least Significant Bits of e.g. the last digital level in the blocks representative of the first video sequence to produce an encoded digital video signal representative of the first video sequence and the second video sequence.

Abstract: In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.

Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b?1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.