Abstract: A random access memory circuit includes a plurality of pixels, each having a light sensitive area and a light blocking layer arranged over at least each of the light sensitive areas. In an alternative embodiment, the circuit includes a plurality of memory elements for storing data. Each memory element may comprise a bit node formed between a photodiode, having a light arranged over the photodiode, and a switching element, where data may be stored. The circuit may also include a plurality of reading and writing circuits for reading and writing data to and from the memory cells.

Abstract: A camera is mounted in a sphere-shaped housing. The housing can be rotated within a base that permits the camera to take multiple images covering a panoramic view. Motion of the housing within the base is detected by motion sensors that provide positional information for allowing the images to be stitched together. The motion sensors are optical mice sensors. Processing circuitry and a power supply may be located within the housing.

Abstract: An image processing device including an encoder processor and a decoder circuit. The encoder processor receives image data from a sensor and encodes the data with padding data if a series of bytes indicative of command sequence occur within the image data. The decoder circuit receives the image data and the padding data, and removes the padding data from within the image data.

Abstract: A camera module may include a mount and a barrel coupled to the mount. One of the barrel and the mount may include a polycarbonate material and the other of the barrel and the mount may include a liquid crystal polymer (LCP) material.

Abstract: An arrangement includes a first part and a second part. The first part includes a memory controller for accessing a memory, at least one first cache memory and a first directory. The second part includes at least one second cache memory configured to request access to said memory. The first directory is configured to use a first coherency protocol for the at least one first cache memory and a second different coherency protocol for the at least one second memory.

Abstract: A radiation sensor of the type having a packaged radiation source and detector, which includes an isolator that blocks propagation within the package of radiation from the source to the detector, in order to improve signal to noise ratio of the sensor. The isolator is formed by appropriately formed surfaces of the package.

Abstract: A memory management device including a plurality of outputs, each output configured to interface to respective one of a plurality of memories; and a controller configured to cause each buffer allocated to the memories to be divided up substantially equally between each of the plurality of memories.

Abstract: A circuit including an initiator of a transaction, an interconnect, and a controller. The controller is configured in response to a condition in a least one first part of the circuit to send a notification via the interconnect to at least one block in a second part of the circuit. The notification includes information about the condition in the first part of the circuit, the condition preventing a response to the transaction from being received by the initiator.

Abstract: A cache memory controller including: a pre-fetch requester configured to issue pre-fetch requests, each pre-fetch request having one of a plurality of different quality of services.

Abstract: A first cache arrangement including an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to the memory request for the second cache arrangement; and a first cache controller; the first cache controller configured such that for the response to the memory request output by the output, the cache memory includes no allocation for data associated with the memory request.

Abstract: A first arrangement including a first interface configured to receive a memory transaction having an address from a second arrangement; a second interface; an address translator configured to determine based on said address if said transaction is for said first arrangement and if so to translate said address or if said transaction is for a third arrangement to forward said transaction without modification to said address to said second interface, said second interface being configured to transmit said transaction, without modification to said address, to said third arrangement.

Abstract: A first arrangement including an interface configured to receive transactions with an address from a second arrangement having a first memory space; a translator configured to translate an address of a first type of received transaction to a second memory space of the first arrangement, the second memory space being different to the first memory space; and boot logic configured to map a boot transaction of the received transactions to a boot region in the second memory space.

Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. This ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.

Abstract: An image sensor has a per-column ADC arrangement including first and second capacitors allowing a comparator circuit to perform correlated double sampling. The capacitors are continuously connected to, respectively, the analog pixel signal and a ramp signal without use of a hold operation. The comparator circuit comprises a differential input being connected to the junction of the two capacitors and being biased by a reference signal. The reference signal is preferably sampled and held from a reference voltage. The use of a differential input as first stage of the comparator addresses problems arising from ground voltage bounce when a large pixel array images a scene with low contrast. Connectivity of the differential input stage allows the ramp signal to see a constant capacitive load thus reduce image artifacts referred to as smear.

Abstract: An imaging system includes a plurality of pixels. A pixel readout circuit produces a plurality of first image frames from those pixels. An image output circuit produces a plurality of second image frames and operates to produce a second image frame from more than one of the first image frames. The pixel readout circuit is enabled to produce the first images frames at a rate faster than the image output circuit produces the second image frames. Through combining first image frames, by averaging or other statistical combinations, the photon shot noise of second image frames is reduced. Photon shot noise affects images with high light levels more than those with low light levels and, as such, the system processing alters the rate of first image frames dependent on the current light levels.

Abstract: A plurality of inputs are configured to receive circuit switched traffic from a plurality of initiators. A plurality of outputs are configured to output said traffic to a network on chip. Each output is associated with a different quality of service traffic. A traffic controller directs the received circuit switched traffic to respective ones of the outputs in dependence on a quality of service associated with the traffic.

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport a plurality of control signals. The number of control signals is greater than a width of the interface. At least one of the first and second dies performs a configurable grouping so as to provide a plurality of groups of control signals. The signals within a group are transmitted across the interface together.

Abstract: A system including input circuitry for receiving from one of a plurality of sources at least one packet stream including a plurality of packets for providing audio, video, private data and/or associated information; at least one output for outputting at least one packet of the at least one packet stream to circuitry arranged to provide an output stream; wherein the system is arranged to provide a tag indicative of the source, the tag being associated with the at least one packet.

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packet includes an address to which data in the packet is to be written. The interface is configured to transport the packet between the dies. A data store is provided to which the data is writable. An interrupt event is determined from data received in several packets.