Patents Assigned to STMicroelectronics SDN, BHD
  • Publication number: 20240120267
    Abstract: A warped semiconductor die is attached onto a substrate such as a leadframe by dispensing a first mass of die attach material onto an area of the substrate followed by dispensing a second mass of die attach material so that the second mass of die attach material provides a raised formation of die attach material. For instance, the second mass may be deposited centrally of the first mass. The semiconductor die is placed onto the first and second mass of die attach material with its concave/convex shape matching the distribution of the die attach material thus effectively countering undesired entrapment of air.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 11, 2024
    Applicants: STMicroelectronics S.r.l., STMicroelectronics SDN BHD
    Inventors: Andrea ALBERTINETTI, Marifi Corregidor CAGUD
  • Patent number: 11887921
    Abstract: A warped semiconductor die is attached onto a substrate such as a leadframe by dispensing a first mass of die attach material onto an area of the substrate followed by dispensing a second mass of die attach material so that the second mass of die attach material provides a raised formation of die attach material. For instance, the second mass may be deposited centrally of the first mass. The semiconductor die is placed onto the first and second mass of die attach material with its concave/convex shape matching the distribution of the die attach material thus effectively countering undesired entrapment of air.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: January 30, 2024
    Assignees: STMicroelectronics S.r.l., STMicroelectronics SDN BHD
    Inventors: Andrea Albertinetti, Marifi Corregidor Cagud
  • Patent number: 11862540
    Abstract: A frame includes leadframe units arranged in a matrix. Each leadframe unit has a die pad and tie bars connected to and extending from the die pad. Each tie bar includes an internal tie bar portion and an external tie bar portion. The internal tie bar portion of at least one tie bar includes a cut separating a part of the internal tie bar portion from the external tie bar portion. An out-of-plane bend in that part forms a mold flow control structure.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: January 2, 2024
    Assignee: STMicroelectronics SDN BHD
    Inventor: Yh Heng
  • Publication number: 20220157681
    Abstract: A lead frame includes a die pad and electrical leads. An integrated circuit chip is mounted to the die pad. An encapsulating package has a perimeter defined by first, second, third and fourth sidewalls. The electrical leads extend from the opposed first and second sidewalls of the package. At least one sidewall of the opposed third and fourth sidewalls of the package includes a V-shaped concavity functioning to increase a creepage distance between the electrical leads at the opposed first and second sidewalls.
    Type: Application
    Filed: October 5, 2021
    Publication date: May 19, 2022
    Applicant: STMicroelectronics SDN BHD
    Inventor: Yang Hong HENG
  • Publication number: 20220068788
    Abstract: A warped semiconductor die is attached onto a substrate such as a leadframe by dispensing a first mass of die attach material onto an area of the substrate followed by dispensing a second mass of die attach material so that the second mass of die attach material provides a raised formation of die attach material. For instance, the second mass may be deposited centrally of the first mass. The semiconductor die is placed onto the first and second mass of die attach material with its concave/convex shape matching the distribution of the die attach material thus effectively countering undesired entrapment of air.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 3, 2022
    Applicants: STMicroelectronics S.r.l., STMicroelectronics SDN BHD
    Inventors: Andrea ALBERTINETTI, Marifi Corregidor CAGUD
  • Publication number: 20210280502
    Abstract: A frame includes leadframe units arranged in a matrix. Each leadframe unit has a die pad and tie bars connected to and extending from the die pad. Each tie bar includes an internal tie bar portion and an external tie bar portion. The internal tie bar portion of at least one tie bar includes a cut separating a part of the internal tie bar portion from the external tie bar portion. An out-of-plane bend in that part forms a mold flow control structure.
    Type: Application
    Filed: February 2, 2021
    Publication date: September 9, 2021
    Applicant: STMicroelectronics SDN BHD
    Inventor: Yh HENG
  • Patent number: 10699990
    Abstract: An integrated circuit (IC) device includes an IC die and a plurality of leads. Each lead includes an unplated proximal end including a first material, and an unplated distal end including the first material. A plated bond wire portion extends between the proximal and distal ends and includes the first material and a plating of a second material thereon. A plurality of bond wires extend between the IC die and the plated bond wire portions of the leads. An encapsulation material surrounds the IC die and bond wires so that the unplated proximal end and plated bond wire portion of each lead are covered by the encapsulation material.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: June 30, 2020
    Assignee: STMicroelectronics SDN BHD
    Inventor: Cheeyang Ng
  • Patent number: 10062639
    Abstract: An integrated circuit (IC) device includes an IC die and a plurality of leads. Each lead includes an unplated proximal end including a first material, and an unplated distal end including the first material. A plated bond wire portion extends between the proximal and distal ends and includes the first material and a plating of a second material thereon. A plurality of bond wires extend between the IC die and the plated bond wire portions of the leads. An encapsulation material surrounds the IC die and bond wires so that the unplated proximal end and plated bond wire portion of each lead are covered by the encapsulation material.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: August 28, 2018
    Assignee: STMicroelectronics SDN BHD
    Inventor: Cheeyang Ng
  • Patent number: 9679832
    Abstract: One or more embodiments are directed to leadframes and leadframe semiconductor packages. One embodiment is directed to copper leadframes with one or more die pads and one more leads with a roughened surface. Covering the roughened surface of the die pad of the leadframe is nanolayer of Silver (Ag). The thickness of the nanolayer preferably has a thickness that corresponds to the roughened surface of the copper leadframe. For instance, in one embodiment, the copper leadframe is roughened to have peaks and valleys that approximately average 10 nanometers and the thickness of the nanolayer is 10 nanometers. Covering a portion of the nanolayer of Ag is a microlayer of Ag, which provides a suitable bonding surface for coupling a semiconductor die to the die pad by an adhesive material.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: June 13, 2017
    Assignee: STMICROELECTRONICS SDN BHD
    Inventor: Yh Heng
  • Publication number: 20110156033
    Abstract: A method and system for tracing die at unit level, comprising: assigning a first identification to a support member including a plurality of die support units; generating a second identification corresponding to a die support unit, the second identification including the first identification and a coordinate of the die support unit within the support member; correlating the second identification to a third identification of a die; attaching the die to the die support unit to generate a packaged die; and assigning the second identification to the packaged die.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Applicants: STMICROELECTRONICS ASIA PACIFIC PTE. LTD., STMICROELECTRONICS SDN BHD
    Inventors: Yohanes Bintang, Enghsiung Ng
  • Patent number: 7075172
    Abstract: A lead-frame for semiconductor devices having a mold with at least one air vent for the resin to seep out of during its injecting into the mold, the air vent being positioned between the upper and lower surface of the frame, wherein the frame provides a through hole positioned at the outlet of the air vent so that, when the resin has solidified, it forms a flash which is in coherence with the surface of the frame.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: July 11, 2006
    Assignees: STMicroelectronics S.r.l., STMicroelectronics SDN, BHD
    Inventors: Andrea Giovanni Cigada, Phui Phoong Chuang
  • Patent number: 6765378
    Abstract: A test handler apparatus, having a treatment area; a testing station in the treatment area; and an output unit connected to an output of the treatment area. An input unit picks singulated or stripped packages and unloads them on carrier boats in a loading zone; a conveyor mechanism transfers the carrier boats from the loading zone through the treatment area to the testing station and from the testing station to the output unit. In practice, the carrier boat forms a universal carrier which is able to contain multiple singulated or strip packages for the purpose of testing. Placing packages onto carriers with standardized dimension allows handler equipment to accommodate the packages in singulated or strip condition.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: July 20, 2004
    Assignee: STMicroelectronics Sdn Bhd
    Inventors: Lee Boon Seng, Tan Kek Yong
  • Publication number: 20030020457
    Abstract: A test handler apparatus, having a treatment area; a testing station in the treatment area; and an output unit connected to an output of the treatment area. An input unit picks singulated or stripped packages and unloads them on carrier boats in a loading zone; a conveyor mechanism transfers the carrier boats from the loading zone through the treatment area to the testing station and from the testing station to the output unit. In practice, the carrier boat forms a universal carrier which is able to contain multiple singulated or strip packages for the purpose of testing. Placing packages onto carriers with standardized dimension allows handler equipment to accommodate the packages in singulated or strip condition.
    Type: Application
    Filed: July 1, 2002
    Publication date: January 30, 2003
    Applicant: STMICROELECTRONICS SDN BHD
    Inventors: Lee Boon Seng, Tan Kek Yong