Patents Assigned to Sumco Techxiv Corporation
  • Patent number: 10553420
    Abstract: A method includes: polishing a semiconductor wafer by a polishing device; measuring a form of the semiconductor wafer by a measuring device before a polished surface of the semiconductor wafer becomes hydrophilic; and setting polishing conditions for the polishing based on a measurement result of the form of the semiconductor wafer by a polishing condition setting unit.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: February 4, 2020
    Assignee: SUMCO TECHXIV CORPORATION
    Inventor: Kenji Yamashita
  • Patent number: 10294583
    Abstract: The sublimation speed of dopant can be precisely controlled without being influenced by a change over time of intra-furnace thermal environment. A dopant supply unit equipped with an accommodation chamber and a supply tube is provided. A sublimable dopant is accommodated. Upon sublimation of the dopant within the accommodation chamber, the sublimed dopant is introduced into a melt. The dopant within the accommodation chamber of the dopant supply unit is heated. The amount of heating by means of heating means is controlled so as to sublime the dopant at a desired sublimation speed. The dopant is supplied to the melt so that the dopant concentration until the first half of a straight body portion of the silicon single crystal is in the state of low concentration or non-addition.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: May 21, 2019
    Assignee: SUMCO TECHXIV CORPORATION
    Inventors: Yasuhito Narushima, Shinichi Kawazoe, Fukuo Ogawa, Masahiro Irokawa, Toshimichi Kubota
  • Patent number: 10233562
    Abstract: A manufacturing method of a single crystal uses a single-crystal pull-up apparatus includes: adding the red phosphorus to the silicon melt so that a resistivity of the single crystal falls in a range from 0.7 m?·cm to 0.9 m?·cm; subjecting an evaluation silicon wafer obtained from the single crystal to a heat treatment in which the evaluation silicon wafer is heated at 1200 degrees C. for 30 seconds in a hydrogen atmosphere; and pull-up the single crystal while appropriately controlling a period for a temperature of the single crystal to be in a range of 570±70 degrees C. so that the number of pits generated on the evaluation silicon wafer becomes 0.1/cm2 or less.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: March 19, 2019
    Assignee: SUMCO TECHXIV CORPORATION
    Inventors: Yasuhito Narushima, Toshimichi Kubota, Fukuo Ogawa, Masayuki Uto
  • Patent number: 10227710
    Abstract: A manufacturing method of a silicon monocrystal uses a monocrystal pulling-up apparatus including: a chamber; a crucible disposed in the chamber and configured to receive dopant-added melt; a pulling-up portion that pulls up a seed crystal after the seed crystal is in contact with the dopant-added melt; a cooler disposed above the crucible to cool a monocrystal that is being grown; and a magnetic field applying unit disposed outside the chamber to apply a horizontal magnetic field to the dopant-added melt. The method includes: during a formation of a shoulder of the silicon monocrystal, starting the formation while moving the cooler downward; stopping the cooler from moving downward at a stop position before a top of the shoulder reaches a level of a lower end of the cooler; and continuing the formation of the shoulder while the cooler is kept at the stop position.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: March 12, 2019
    Assignee: SUMCO TECHXIV CORPORATION
    Inventors: Yasuhito Narushima, Toshimichi Kubota, Masayuki Uto
  • Patent number: 9975217
    Abstract: A diffusion plate includes a plate member facing an opening end of a supply pipe with a thickness direction thereof substantially parallel with a supply direction of a supply fluid. The plate member is rotatable around a rotation axis substantially parallel with the thickness direction and has a diffusion hole, penetrating in the thickness direction at a position other than a rotation center of the plate member. The diffusion hole has a wall surface defined at a rear side in a rotation direction and has a first wall surface end defined in a facing surface facing the supply pipe, at a rearmost in the rotation direction and a second wall surface end defined in a non-facing surface at a rearmost in the rotation direction. The wall surface is inclined with the first wall surface end being at a front side of the second wall surface end in the rotation direction.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 22, 2018
    Assignee: SUMCO TECHXIV CORPORATION
    Inventor: Yoshinobu Nishimura
  • Patent number: 9876078
    Abstract: An amount of warp of a wafer is not only reduced, but the amount of warp of the wafer is also accurately controlled to a desired amount. The present invention relates to a method for slicing a semiconductor single crystal ingot, by which a cylindrical semiconductor single crystal ingot is bonded to and held by a holder in a state where the ingot is rotated at a predetermined rotation angle around a crystal axis of the ingot different from a center axis of a cylinder of this ingot and the ingot is sliced by a cutting apparatus in this state. The predetermined rotation angle at the time of bonding and holding the ingot with the use of the holder in such a manner that an amount of warp of a wafer sliced out by the cutting apparatus becomes a predetermined amount.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 23, 2018
    Assignee: SUMCO TECHXIV CORPORATION
    Inventor: Hiroshi Noguchi
  • Patent number: 9758871
    Abstract: A method of manufacturing an epitaxial wafer in which an epitaxial layer is grown over a main surface of a silicon wafer placed substantially horizontally on a susceptor is provided. The method comprises: a growing step of the epitaxial layer; and a cooling step of cooling the epitaxial wafer having the epitaxial layer. The cooling step comprises: a wafer measurement step of measuring a temperature of the epitaxial wafer; a susceptor measurement step of measuring a temperature of the susceptor; and a control step of controlling a heater capable of heating at least the susceptor or the epitaxial wafer such that difference between a temperature of the epitaxial wafer and a temperature of the susceptor is within a predetermined range.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: September 12, 2017
    Assignee: SUMCO TECHXIV CORPORATION
    Inventor: Kazuhiro Narahara
  • Patent number: 9758899
    Abstract: Disclosed is a silicon single crystal pull-up apparatus that can grow a silicon single crystal having a desired electrical resistivity, to which a sublimable dopant has been reliably added, regardless of the length of the time necessary for the formation of a first half part of a straight body part in a silicon single crystal. Also disclosed is a process for producing a silicon single crystal. The silicon single crystal pull-up apparatus pulls up a silicon single crystal from a melt by a Czochralski method. The silicon single crystal pull-up apparatus comprises a pull-up furnace, a sample chamber that is externally mounted on the pull-up furnace and houses a sublimable dopant, a shielding mechanism that thermally shields the pull-up furnace and the sample chamber, and supply means that, after the release of shielding of the shielding mechanism, supplies the sublimable dopant into the melt.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 12, 2017
    Assignee: SUMCO TECHXIV CORPORATION
    Inventor: Tomohiro Fukuda
  • Patent number: 9755022
    Abstract: An epitaxial silicon wafer includes a silicon wafer added with phosphorus so that resistivity of the silicon wafer falls at or below 0.9 m?·cm, an epitaxial film formed on a first side of the silicon wafer, and an oxidation film formed on a second side of the silicon wafer opposite to the first side, wherein an average number of Light Point Defect of a size of 90 nm or more observed on a surface of the epitaxial film is one or less per square centimeter.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: September 5, 2017
    Assignees: SUMCO TECHXIV CORPORATION, SUMCO CORPORATION
    Inventors: Tadashi Kawashima, Naoya Nonaka, Masayuki Shinagawa, Gou Uesono
  • Publication number: 20170029975
    Abstract: A manufacturing method of a silicon monocrystal uses a monocrystal pulling-up apparatus including: a chamber; a crucible disposed in the chamber and configured to receive dopant-added melt; a pulling-up portion that pulls up a seed crystal after the seed crystal is in contact with the dopant-added melt; a cooler disposed above the crucible to cool a monocrystal that is being grown; and a magnetic field applying unit disposed outside the chamber to apply a horizontal magnetic field to the dopant-added melt.
    Type: Application
    Filed: June 28, 2016
    Publication date: February 2, 2017
    Applicant: SUMCO TECHXIV CORPORATION
    Inventors: Yasuhito NARUSHIMA, Toshimichi KUBOTA, Masayuki UTO
  • Patent number: 9425264
    Abstract: A method includes: a backside-oxidation-film-formation step in which an oxidation film is formed on a backside of a silicon wafer; a backside-oxidation-film-removal step in which the oxidation film provided at an outer periphery of the silicon wafer is removed; an argon-annealing step in which the silicon wafer after the backside-oxidation-film-removal step is subjected to a heat treatment in an argon gas atmosphere at a temperature in a range from 1200 to 1220 degrees C. for 60 minutes or more and 120 minutes or less; and an epitaxial-film-formation step in which an epitaxial film is formed on a surface of the silicon wafer after the argon-annealing step.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: August 23, 2016
    Assignees: SUMCO CORPORATION, SUMCO TECHXIV CORPORATION
    Inventors: Tadashi Kawashima, Naoya Nonaka, Masayuki Shinagawa, Gou Uesono
  • Publication number: 20160196966
    Abstract: A method includes: polishing a semiconductor wafer by a polishing device; measuring a form of the semiconductor wafer by a measuring device before a polished surface of the semiconductor wafer becomes hydrophilic; and setting polishing conditions for the polishing based on a measurement result of the form of the semiconductor wafer by a polishing condition setting unit.
    Type: Application
    Filed: May 29, 2014
    Publication date: July 7, 2016
    Applicant: SUMCO TECHXIV CORPORATION
    Inventor: Kenji YAMASHITA
  • Publication number: 20160176020
    Abstract: A diffusion plate includes a plate member facing an opening end of a supply pipe with a thickness direction thereof substantially parallel with a supply direction a supply fluid. The plate member is rotatable around a rotation axis substantially parallel with the thickness direction and has a diffusion hole, penetrating in the thickness direction at a position other than a rotation center of the plate member. The diffusion hole has a wall surface defined at a rear side in a rotation direction and has a first wall surface end defined in a facing surface facing the supply pipe, at a rearmost in the rotation direction and a second wall surface end defined in a non-facing surface at a rearmost in the rotation direction. The wall surface is inclined with the first wall surface end being at a front side of the second wall surface end in the rotation direction.
    Type: Application
    Filed: April 25, 2014
    Publication date: June 23, 2016
    Applicant: SUMCO TECHXIV CORPORATION
    Inventor: Yoshinobu NISHIMURA
  • Publication number: 20160102418
    Abstract: A manufacturing method of a single crystal uses a single-crystal pull-up apparatus includes: adding the red phosphorus to the silicon melt so that a resistivity of the single crystal falls in a range from 0.7 m?·cm to 0.9 m?·cm; subjecting an evaluation silicon wafer obtained from the single crystal to a heat treatment in which the evaluation silicon wafer is heated at 1200 degrees C. for 30 seconds in a hydrogen atmosphere; and pull-up the single crystal while appropriately controlling a period for a temperature of the single crystal to be in a range of 570±70 degrees C. so that the number of pits generated on the evaluation silicon wafer becomes 0.1/cm2 or less.
    Type: Application
    Filed: April 15, 2014
    Publication date: April 14, 2016
    Applicant: SUMCO TECHXIV CORPORATION
    Inventors: Yasuhito NARUSHIMA, Toshimichi KUBOTA, Fukuo OGAWA, Masayuki UTO
  • Patent number: 9305850
    Abstract: A method and an apparatus of etching a semiconductor wafer are provided. The etching apparatus of a semiconductor wafer having a marker inside includes: a monitoring device capable of monitoring a surface of the semiconductor wafer so as to detect the marker; a nozzle capable of jetting a mixed gas that contains hydrogen fluoride and ozone onto the surface of the semiconductor wafer; a regulator capable of adjusting at least one of hydrogen fluoride concentration and ozone concentration in the mixed gas; and a controller capable of determining whether the marker is detected by the monitoring device and terminating the etching process.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: April 5, 2016
    Assignee: SUMCO TECHXIV CORPORATION
    Inventors: Kazuaki Kozasa, Tomonori Kawasaki
  • Patent number: 9293318
    Abstract: A method of manufacturing a semiconductor wafer includes: rough-polishing front and back surfaces of the semiconductor wafer; mirror-polishing a chamfered portion of the rough-polished semiconductor wafer; performing mirror finish polishing on the front surface or both the front and back surfaces of the semiconductor wafer having the mirror-polished chamfered portion; and forming an oxide film on an entire surface of the semiconductor wafer after the mirror-polishing of the chamfered portion and before the mirror finish polishing.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: March 22, 2016
    Assignee: SUMCO TECHXIV CORPORATION
    Inventor: Kenji Yamashita
  • Publication number: 20150380493
    Abstract: An epitaxial silicon wafer includes a silicon wafer added with phosphorus so that resistivity of the silicon wafer falls at or below 0.9 m?·cm, an epitaxial film formed on a first side of the silicon wafer, and an oxidation film formed on a second side of the silicon wafer opposite to the first side, wherein an average number of Light Point Defect of a size of 90 nm or more observed on a surface of the epitaxial film is one or less per square centimeter.
    Type: Application
    Filed: September 10, 2015
    Publication date: December 31, 2015
    Applicants: SUMCO CORPORATION, SUMCO TECHXIV CORPORATION
    Inventors: Tadashi KAWASHIMA, Naoya NONAKA, Masayuki SHINAGAWA, Gou UESONO
  • Patent number: 9212431
    Abstract: A graphite member utilized in a pulling device for pulling a silicon single crystal is provided. An edge part of the graphite member is rounded off which is exposed to a reactive gas. The graphite member may comprise: a plate part having a thickness of ‘t’ wherein a curvature radius of ‘r’ satisfies the formula: t/8?r?t/4.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: December 15, 2015
    Assignee: SUMCO TECHXIV CORPORATION
    Inventors: Shinichi Kawazoe, Fukuo Ogawa, Yasuhito Narushima, Tsuneaki Tomonaga, Toshimichi Kubota
  • Patent number: 9181631
    Abstract: Provided is a silicon crystalline material, which is manufactured by a CZ method to be used as a material bar for manufacturing a silicon single crystal by an FZ method and has a grasping section for being loaded in a crystal growing furnace employing the FZ method without requiring mechanical processing. A method for manufacturing such silicon crystalline material is also provided. The silicon crystalline material is manufactured by the silicon crystal manufacturing method employing the CZ method and is provided with the grasping section, which is manufactured in a similar way as a shoulder portion, a straight body portion and a tail portion in a silicon crystal growing step employing the CZ method, and is loaded in a single crystal manufacturing apparatus employing the FZ method to grow single crystals. A seed-crystal used in the silicon crystal manufacture employing the CZ method is used as the grasping section.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: November 10, 2015
    Assignee: SUMCO TECHXIV CORPORATION
    Inventors: Shinji Togawa, Ryosuke Ueda
  • Patent number: 9080251
    Abstract: A velocity of Ar gas flow passing through between a lower end of a cylindrical body and a thermal shielding body is influenced by arrangement of a pulling path of single crystal silicon, a cylindrical body, and a thermal shielding body. Accordingly, the velocity of the Ar gas flow passing through between a lower end of the cylindrical body and the thermal shielding body is controlled by adjusting a relative position of the pulling path of the single crystal silicon, the cylindrical body, and the thermal shielding body. As described above, dust falling off to silicon melt can be reduced, thereby preventing deterioration in quality of the single crystal silicon.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: July 14, 2015
    Assignee: SUMCO TECHXIV CORPORATION
    Inventors: Makato Kamogawa, Koichi Shimomura, Yoshiyuki Suzuki, Daisuke Ebi