Patents Assigned to Suniva, Inc.
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Patent number: 9153728Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a substrate comprising a base layer and introducing n-type dopant to the front surface of the base layer by ion implantation. The substrate may be annealed by heating the substrate to a temperature to anneal the implant damage and activate the introduced dopant, thereby forming an n-type doped layer into the front surface of the base layer. Oxygen may be introduced during the annealing step to form a passivating oxide layer on the n-type doped layer. Back contacts may be screen-printed on the back surface of the base layer, and a p-type doped layer may be formed at the interface of the back surface of the base layer and the back contacts during firing of the back contacts. The back contacts may provide an electrical connection to the p-type doped layer.Type: GrantFiled: January 9, 2012Date of Patent: October 6, 2015Assignee: Suniva, Inc.Inventors: Ajeet Rohatgi, Vijay Yelundur, Vinodh Chandrasekaran, Preston Davis, Ben Damiani
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Patent number: 8945976Abstract: A thin silicon solar cell is described. An example solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer. A final layer of transparent conductive oxide is formed on both sides. Metal contacts are applied to the transparent conductive oxide.Type: GrantFiled: November 30, 2011Date of Patent: February 3, 2015Assignee: Suniva, Inc.Inventors: Daniel L. Meier, Ajeet Rohatgi
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Patent number: 8921968Abstract: Solar cells and methods for their manufacture are disclosed. An example solar cell may comprise a substrate comprising a p-type base layer and an n-type selective emitter layer formed over the p-type base layer. The n-type selective emitter layer may comprise one or more first doped regions comprising implanted dopant and one or more second doped regions comprising diffused dopant. The one or more first doped regions may be more heavily doped than the one or more second doped regions. A p-n junction may be formed at the interface of the base layer and the selective emitter layer, such that the p-n junction and the selective emitter layer are both formed during a single anneal cycle.Type: GrantFiled: November 21, 2011Date of Patent: December 30, 2014Assignee: Suniva, Inc.Inventors: Ajeet Rohatgi, Vijay Yelundur, Preston Davis, Vinodh Chandrasekaran, Ben Damiani
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Publication number: 20140332059Abstract: A mounting system for mounting a plurality of solar panels is provided. In one aspect, the mounting system has plurality of panel modules and at least one of: a means for selectively securing a pair of adjacently positioned panel modules to a support structure in an edge-to-edge relationship along a mounting axis that is transverse to the coupling axis, and a means for selectively locking a distal end of one pair of mounting members of one panel module to a proximal end of another pair of mounting members of an adjoining panel module to form at least a portion of one coupled panel module that is adjoined end-to-end along a coupling axis that is transverse to the mounting axis.Type: ApplicationFiled: May 9, 2014Publication date: November 13, 2014Applicant: Suniva, Inc.Inventors: Stephen Patrick Shea, Gregory Tyrone Jones
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Publication number: 20140238478Abstract: Back junction solar cells having improved emitter layer coverage and methods for their manufacture are disclosed. In one embodiment, a back junction solar cell includes an n-type base layer having an emitter layer formed from a first p-type doped region (e.g., formed by liquid phase epitaxial regrowth) and a second p-type doped region (e.g., formed by ion implantation) that extends beyond the first region. In various embodiments, this configuration permits the first p-type doped region to be formed with a border between it and the edges of the wafer (e.g., to prevent inadvertent shunting of the cell), while the second p-type doped region extends the emitter layer to improve emitter layer coverage. In certain embodiments, the second doped p-type region may extend to the edges of the wafer's n-type base layer.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Applicant: SUNIVA, INC.Inventors: Daniel L Meier, Xiaoyan Wang, Adam M Payne, Atul Gupta
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Publication number: 20140090702Abstract: Various embodiments of the present invention are directed to a reduced-area bus bar for collecting current from contacts on the surface of a solar cell. According to various embodiments described herein, a reduced-area bus bar is provided having a width that varies at various points along its longitudinal axis. In particular, the larger width portions of the reduced-area bus bar are configured to provide sufficient pull strength when an interconnecting ribbon is soldered along the bus bar, while the smaller width portions of the reduced-area bus bar enable a reduction in the material required to form the bus bar. Additionally, various embodiments are contemplated in which the reduced-area bus bar comprises a series of segments disposed in a spaced-apart relationship along the bus bar's longitudinal axis.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: Suniva, Inc.Inventors: Atul Gupta, Vinodh Chandrasekaran, John Roberts
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Publication number: 20130247981Abstract: Solar cells, solar modules, and methods for their manufacture are disclosed. An example method may comprise forming a dielectric layer on at least one or more edges of a substrate, and then introducing dopant to at least one surface of the substrate. The substrate may be subjected to a heating process to at least drive the dopant to a predefined depth, thereby forming at least one of an emitter layer and a surface field layer. In the example method, the dielectric layer may not be removed during a subsequent manufacturing process. Associated solar cells and solar modules are also provided.Type: ApplicationFiled: March 21, 2012Publication date: September 26, 2013Applicant: SUNIVA, INC.Inventors: VIJAY YELUNDUR, ATUL GUPTA, JASEN MOFFITT
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Patent number: 8241945Abstract: Solar cells and methods for fabrication thereof are provided. A method may include forming a via through at least one dielectric layer formed on a semiconductor wafer by using a laser to ablate a region of the at least one dielectric layer such that at least a portion of the surface of the semiconductor wafer is exposed by the via. The method may further include applying a self-doping metal paste to the via. The method may additionally include heating the semiconductor wafer and self-doping metal paste to a temperature sufficient to drive at least some dopant from the self-doping metal paste into the portion of the surface of the semiconductor wafer exposed by the via to form a selective emitter region and a contact overlying and self-aligned to the selective emitter region.Type: GrantFiled: February 8, 2010Date of Patent: August 14, 2012Assignee: Suniva, Inc.Inventors: Adam M. Payne, Daniel L. Meier, Vinodh Chandrasekaran
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Publication number: 20120171806Abstract: A thin silicon solar cell is described. An example solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer. A final layer of transparent conductive oxide is formed on both sides Metal contacts are applied to the transparent conductive oxide.Type: ApplicationFiled: November 30, 2011Publication date: July 5, 2012Applicant: SUNIVA, INC.Inventors: DANIEL L. MEIER, AJEET ROHATGI
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Publication number: 20120125416Abstract: Solar cells and methods for their manufacture are disclosed. An example solar cell may comprise a substrate comprising a p-type base layer and an n-type selective emitter layer formed over the p-type base layer. The n-type selective emitter layer may comprise one or more first doped regions comprising implanted dopant and one or more second doped regions comprising diffused dopant. The one or more first doped regions may be more heavily doped than the one or more second doped regions. A p-n junction may be formed at the interface of the base layer and the selective emitter layer, such that the p-n junction and the selective emitter layer are both formed during a single anneal cycle.Type: ApplicationFiled: November 21, 2011Publication date: May 24, 2012Applicant: SUNIVA, INC.Inventors: AJEET ROHATGI, VIJAY YELUNDUR, PRESTON DAVIS, VINODH CHANDRASEKARAN, BEN DAMIANI
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Publication number: 20120107998Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a substrate comprising a base layer and introducing n-type dopant to the front surface of the base layer by ion implantation. The substrate may be annealed by heating the substrate to a temperature to anneal the implant damage and activate the introduced dopant, thereby forming an n-type doped layer into the front surface of the base layer. Oxygen may be introduced during the annealing step to form a passivating oxide layer on the n-type doped layer. Back contacts may be screen-printed on the back surface of the base layer, and a p-type doped layer may be formed at the interface of the back surface of the base layer and the back contacts during firing of the back contacts. The back contacts may provide an electrical connection to the p-type doped layer.Type: ApplicationFiled: January 9, 2012Publication date: May 3, 2012Applicant: SUNIVA, INC.Inventors: AJEET ROHATGI, VIJAY YELUNDUR, VINODH CHANDRASEKARAN, PRESTON DAVIS, BEN DAMIANI
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Patent number: 8110431Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a p-type doped silicon substrate and introducing n-type dopant to a first and second region of the front surface of the substrate by ion implantation so that the second region is more heavily doped than the first region. The substrate may be subjected to a single high-temperature anneal cycle to activate the dopant, drive the dopant into the substrate, produce a p-n junction, and form a selective emitter. Oxygen may be introduced during the single anneal cycle to form in situ front and back passivating oxide layers. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. Associated solar cells are also provided.Type: GrantFiled: June 3, 2010Date of Patent: February 7, 2012Assignee: Suniva, Inc.Inventors: Ajeet Rohatgi, Vijay Yelundur, Vinodh Chandrasekaran, Preston Davis, Ben Damiani
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Patent number: 8071418Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a silicon substrate and introducing dopant to one or more selective regions of the front surface of the substrate by ion implantation. The substrate may be subjected to a single high-temperature anneal cycle. Additional dopant atoms may be introduced for diffusion into the front surface of the substrate during the single anneal cycle. A selective emitter may be formed on the front surface of the substrate such that the one or more selective regions of the selective emitter layer are more heavily doped than the remainder of the selective emitter layer. Associated solar cells are also provided.Type: GrantFiled: June 3, 2010Date of Patent: December 6, 2011Assignee: Suniva, Inc.Inventors: Ajeet Rohatgi, Vijay Yelundur, Preston Davis, Vinodh Chandrasekaran, Ben Damiani
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Publication number: 20090211627Abstract: A thin silicon solar cell is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer at temperatures below approximately 400 degrees Celsius to reduce the loss of passivation properties of the amorphous silicon. A final layer of transparent conductive oxide is formed on both sides at approximately 165 degrees Celsius. Metal contacts are applied to the transparent conductive oxide. The low temperatures and very thin material layers used to fabricate the outer layers of used to fabricate the outer layers of the solar cell protect the thin wafer from excessive stress that may lead to deforming the wafer.Type: ApplicationFiled: February 25, 2008Publication date: August 27, 2009Applicant: Suniva, Inc.Inventors: Daniel L. Meier, Ajeet Rahatgi
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Publication number: 20090211623Abstract: A thin silicon solar cell is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer at temperatures below approximately 400 degrees Celsius to reduce the loss of passivation properties of the amorphous silicon. A final layer of transparent conductive oxide is formed on both sides at approximately 165 degrees Celsius. Metal contacts are applied to the transparent conductive oxide. The low temperatures and very thin material layers used to fabricate the outer layers of used to fabricate the outer layers of the solar cell protect the thin wafer from excessive stress that may lead to deforming the wafer.Type: ApplicationFiled: February 25, 2008Publication date: August 27, 2009Applicant: Suniva, Inc.Inventors: Daniel L. Meier, Ajeet Rohatgi
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Publication number: 20090215218Abstract: A thin silicon solar cell is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer at temperatures below approximately 400 degrees Celsius to reduce the loss of passivation properties of the amorphous silicon. A final layer of transparent conductive oxide is formed on both sides at approximately 165 degrees Celsius. Metal contacts are applied to the transparent conductive oxide. The low temperatures and very thin material layers used to fabricate the outer layers of used to fabricate the outer layers of the solar cell protect the thin wafer from excessive stress that may lead to deforming the wafer.Type: ApplicationFiled: February 25, 2008Publication date: August 27, 2009Applicant: Suniva, Inc.Inventors: Daniel L. Meier, Ajeet Rohatgi