Abstract: An on-chip resistor correction circuit includes a first MOS transistor connected between VDD and a reference resistor, the other end of the reference resistor being grounded; an operational amplifier for outputting a first control signal based on a reference voltage and a voltage of the reference resistor; a second MOS transistor connected between VDD and a reference node; a branch where each of the on-chip resistors is located is controllably connected between the reference node and ground; a comparator for generating a comparison signal based on the voltage of the reference node and the reference voltage; and a controller for generating a control signal under the action of the comparison signal to control the branch where each of the on-chip resistors is located to turn on or off.

Abstract: A delay line structure and a delay jitter correction method thereof are provided. The delay line structure comprises N delay units and N selectors. An output end of the N?1th delay unit is connected to a first input end of the N?1th selector and an input end of the Nth delay unit respectively, the N?1th selector inputs the N?1th selection signal, an output end of the Nth delay unit is connected to a first input end of the Nth selector, an output end of the Nth selector is connected to a second input end of the N?1th selector, and the Nth selector inputs the Nth selection signal. The time delay units and the selectors are stacked forwards according to the above-mentioned rule until the input ends of the first time delay units are connected with input signals and the output ends of the first selectors are connected with output signals.