Abstract: A device for data stream analyzing that is able to recognize different data streams and then start processors or functionalities to store or check data in a data stream. The device includes a processor means and a program memory, making it possible to parse a data stream in a way that is controlled by an interchangeable program. There will be no need for changing the hardware. This could save time and money for companies responsible for providing, maintaining and updating network switches. The device also includes a multiplexable data stream delayline for receiving the data streams, and multiplexing means for connecting different parts of the data stream to the processor.

Abstract: The invention relates to a method for flow control in a switch and a switch controlled thereby. In order to ensure that no or few packets are dropped in a switch because of a congested internal memory, pause frames or stop command messages are sent to upstream senders. When to send pause frames are determined by monitoring the buffer contents of the switch and estimating the total expected contents of the links between the senders and the switch. The pause frames are sent to the most offending senders, i.e. the senders causing the largest queues in the switch.

Abstract: A device for data stream analyzing that is able to recognize different data streams and then start processors or functionalities to store or check data in a data stream. The device includes a processor means and a program memory, making it possible to parse a data stream in a way that is controlled by an interchangeable program. There will be no need for changing the hardware. This could save time and money for companies responsible for providing, maintaining and updating network switches. The device also includes a multiplexable data stream delayline for receiving the data streams, and multiplexing means for connecting different parts of the data stream to the processor means.

Abstract: The invention relates to a method and means for managing packet queues in switches. The switch has a shared memory split in a small internal memory and a large external memory. There is limited bandwidth to the external memory. The method comprises the steps of dividing a data stream incoming on the input ports intended for respective output ports into two parts, of which the first part is to be sent to an internal queue belonging to at least one output port and the second part is to be sent to the external memory. The incoming data stream may be identified as belonging to flow groups and the division of the data stream is then performed e.g. such that flow groups with a higher priority than a division threshold are sent to said internal queues in the first part, while flow groups with priority lower than said threshold are sent to the external memory in the second part.

Abstract: The invention relates to a scheduler method and device for handling output queues in a switch. The invention incorporates a number of co-operating techniques such as weighted and deficit driven round-robin and interleaving. The invention provides a scheduling method in a switch in which an input data stream is received and stored in a number of output queues, the method comprising the steps of: polling all queues in order; if the polled queue contains data, refilling a deficit value indicating a maximum amount of data that may be sent from this queue; if the deficit value permits, sending data, and decreasing the deficit value a corresponding amount for the polled queue, else disabling the queue; if any queue is permitted to send after all the queues have been polled, going to a local round, else start polling the first queue of the order again. The invention enables e.g. priority treatment of queues, fairness with regard to varying packet lengths and avoids burstiness.

Abstract: The invention relates to a buffer memory, method and a buffer controller for queue management usable in an ATM switch. An object of the invention is to achieve a high frequency throughput of data cells in the buffer memory. This object is achieved by using a buffer memory which is organized as 256*(424+8) SRAM-cells. The memory is used for holding ten queues, one for each incoming channel and two free-queues containing idle cells.

Abstract: The invention relates to a method and an arrangement for multicasting, i.e. point to multipoint transmission of a data packet. A packet is copied and transmitted to multiple addresses. In the multicasting arrangement, switch core and input and output port are connected to input and output links, respectively, for transmitting data packets. According to the invention, the input port is adapted to detect a multicasting packet received on an input link or from an output port and send the multicasting packet to an output port. The output port is adapted to detect the multicasting packet, copy the data packet, modify an address portion of the multicasting packet, send one packet on the output link and return one packet with the modified address portion to an input port. Preferably, the input port and the output port are integrated in a link interface having a direct channel for returning the data packet.

Abstract: The present invention provides a content addressable memory (CAM) circuit that includes at least one row of memory cells storing data to be subjected to search data for a compare operation, with the cells in each row being inter-connected by a match line. Each cell can, if the search data does not match the stored data, discharge the match line in an evaluation operation. According to the present invention, a match line is partitioned into a least two segments, each segment having a first unit for precharging and evaluating the match line segment and a second unit for determining the result of the evaluation operation. The compare operation of the second and any subsequent segments is performed and the corresponding matchline segment involved only if the result of the compare operation of the respective preceding segment indicates a data match.