Abstract: The present invention relates to a CAM/RAM memory device with scalable structure with a CAM (Content Addressable Memory) mode and a RAM (Random Access Memory) mode, where selectable parts of the memory cells can be masked off for the CAM mode and reading and writing may be performed directly through an address decoder in the RAM mode. The memory is divided into blocks (1), each having a number of rows. The address decoder (2) is connected by word lines (3) to the cells in a row of the blocks (1) and a multiplexer (4) is adapted to select which block of memory to read data from. The memory device further includes a blocking means adapted to block the word lines when the memory device is in a CAM match read mode, such that several parallel hits in different blocks may be read without generating an invalid read-out.