Patents Assigned to Symmetricom, Inc.
  • Patent number: 5832375
    Abstract: A satellite navigation receiver uses common dual-conversion superheterodyne and frequency synthesiser circuitry for receiving signals from both the GPS and the GLONASS satellite navigation systems. Successive first and second frequency down-converters in the receiver chain are fed by first and second local oscillator signals which are both variable in frequency such that the frequency of the first local oscillator signal is an integral multiple (preferably 8) of the second local oscillator signal. This relationship is provided by a binary divider (32) at least a portion of which may form part of a digital frequency synthesiser loop.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: November 3, 1998
    Assignee: SymmetriCom, Inc.
    Inventors: Oliver P. Leisten, Raymond J. Hasler
  • Patent number: 5828670
    Abstract: Apparatus and methods for distributing synchronization throughout a network is disclosed. The distribution of the synchronization is through the use of generating a reference timing signal, and by counting the line clock pulses between the start of a frame and the timing reference signal pulse at a first office and that count is then encoded and transmitted to the next office. At the next office, the transmitted count is decoded and used for regenerating synchronization by counting a number of received line clock pulses from the start of the frame to regenerate the reference timing signal. Particular criteria for selecting the frequencies for the timing reference signal are disclosed.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: October 27, 1998
    Assignee: Symmetricom, Inc.
    Inventors: Madihally Narasimha, Kishan Shenoi
  • Patent number: 5764704
    Abstract: Demodulating FM signals using digital signal processing extracts a carrier signal from digitized channel signals, multiplies the digital channel signal with this extracted carrier signal, and further filters out the carrier signal to produce the demodulated signal. The DSP technique first down converts a group of channels to baseband which are then processed through an A/D converter to produce a digitized composite signal. A bank of bandpass filters, typically based on FFT processors, applied to the composite signal produce (a group of) digitized channel signal(s). The digitized channel signal is then demodulated by recovering a carrier signal by digitally filtering, for example, using a Hilbert bandpass filter, the channel signal and digitally filtering the product of the carrier signal and the channel signal to recover the modulating voice signals.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: June 9, 1998
    Assignee: SymmetriCom, Inc.
    Inventor: Kishan Shenoi
  • Patent number: 5751777
    Abstract: A dual locked loop is disclosed comparing preferably a GPS signal with an E1 signal and the E1 signal with the output of the loop. The GPS signal is low pass filtered to provide a low pass filtered GPS versus E1 signal that is used as a calibration for a closed loop having a second low pass filter for filtering the comparisons of the E1 and the output signal. By appropriately selecting the filter parameters, the output stability can track the stability of the local oscillator driving the NCO for short term stability, the medium term stability of the E1 signal and the long term stability of the GPS signal.
    Type: Grant
    Filed: May 3, 1996
    Date of Patent: May 12, 1998
    Assignee: SymmetriCom, Inc.
    Inventor: George Zampetti
  • Patent number: 5646519
    Abstract: A digital phase detector composed of: a digitally controllable signal delay device having a signal input, a signal output and a control input, the delay device being operative for conducting a signal from the signal input to the signal output with a time delay having a duration determined by a control signal supplied to the control input, the signal input being connected to receive either an input signal or a digital local clock signal; a phase relation detector connected to receive a first input signal from the signal output of the signal delay device and a second input signal constituted by the one of the input signal and the digital local clock signal which is not received by the signal input of the signal delay device, for periodically comparing the phases of the first and second input signals and for producing a binary output signal composed of a succession of signal segments, each segment having a first value when the first input signal is leading the second input signal in phase and a second value when
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 8, 1997
    Assignee: Symmetricom, Inc.
    Inventors: Michael M. Hamilton, Morley M. Merriss, George P. Zampetti
  • Patent number: 5638379
    Abstract: Apparatus and methods for distributing synchronization throughout a network is disclosed. The distribution of the synchronization is through the use of generating a reference timing signal, and by counting the line clock pulses between the start of a frame and the timing reference signal pulse at a first office and that count is then encoded and transmitted to the next office. At the next office, the transmitted count is decoded and used for regenerating synchronization by counting a number of received line clock pulses from the start of the frame to regenerate the reference timing signal. Particular criteria for selecting the frequencies for the timing reference signal are disclosed.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 10, 1997
    Assignee: Symmetricom, Inc.
    Inventors: Madihally Narasimha, Kishan Shenoi
  • Patent number: 5606736
    Abstract: A satellite navigation receiver uses common dual-conversion superheterodyne and frequency synthesizer circuitry for receiving signals from both the GPS and the GLONASS satellite navigation systems. Successive first and second frequency down-converters in the receiver chain are fed by first and second local oscillator signals which are both variable in frequency such that the frequency of the first local oscillator signal is an integral multiple (preferably 8) of the second local oscillator signal. This relationship is provided by a binary divider (32) at least a portion of which may form part of a digital frequency synthesizer loop.
    Type: Grant
    Filed: November 9, 1994
    Date of Patent: February 25, 1997
    Assignee: SymmetriCom, Inc.
    Inventors: Raymond J. Hasler, Oliver P. Leisten
  • Patent number: 5457729
    Abstract: A communication network signalling system couples a signal transfer point to a plurality of channel banks through links which include link monitor and test units. The link monitor and test units, which monitor the links in a passive, non-obtrusive manner and which at the same time are capable of being serially coupled into the link so as to insert signals in series with the link and to otherwise accomplish in-depth link testing and analysis, each include a pair of channel units coupled to opposite portions of an associated link and which are coupled together through a metallic through connection in the form of a normally unenergized relay. The metallic through connection provided by the relay maintains the signal path through the link during a variety of fault conditions, while at the same time permitting electronic portions of the channel units to be cross-connected to accomplish monitoring and testing functions.
    Type: Grant
    Filed: February 7, 1995
    Date of Patent: October 10, 1995
    Assignee: Symmetricom, Inc.
    Inventors: Gary L. Hamann, Robert P. Hamilton