Abstract: An apparatus and method for measuring errors and event occurrences in a multi-valued data stream by using a dual decision bit error rate tester is disclosed. The Bit error rate tester (BERT) includes a plurality of decision circuits operative to provide a respective bit decision output signal in response to an input signal. The bit decision output signal magnitude information of a signal under test as measured over a sample window period. A comparator circuit is coupled to each of the plurality of decision circuits, and is operative to provide an event occurrence signal in response to the bit decision output signals from each of the plurality of decision circuits. The BERT provides the ability to supply additional information and feedback about the behavior and performance of the targeted device or subsystem being tested and to perform error measurements in non-constrained data (i.e. live data).

Abstract: A testing circuit includes a signal generator operative to provide a control signal in response to a reference clock signal. The control signal may include both alignment and timing information operative to synchronize the timing and output of the signal generator with a device under test. A clock recovery instrument is electrically coupled to the signal generator. The clock recovery instrument generates the reference clock signal in response to a clock signal from the device under test. The reference clock signal is synchronized with the clock signal from the device under test such that signal generator operation is synchronized with the device under test independent of the behavior of the device under test.

Abstract: Disclosed herein is a method and apparatus used to the measure duty cycle of a clocking waveform utilizing minimal hardware and achieving high accuracy. This invention utilizes digital sampling of the signal to be measured at a rate that can be significantly lower then the clocking frequency of the signal to be measured. It accomplishes broad-band, multi-frequency use by using a time-varying frequency for the sampling clock to make sure that the sampling clock is asynchronous with the frequency of the clocking signal to be measured. The average ratio of the sampled ones (or zeros) as compared to the total number of samples is then computed to derive the measurement of duty cycle.

Abstract: Disclosed herein is a method and apparatus used to detect phase error information between edges of an input data signal and a clock signal for use at ultra-high frequencies and where linear phase error information is required. This invention extends the usefulness of a given integrated circuit logic technology to twice the frequency range of application while maintaining the desired linear phase error measurement operation. Flip flops are used to sample the data input signal with the clocking signal and processing is done separately for rising and falling data edges. Analog recombination of phase error information from both edges is then done in a fashion that is not limited by the integrated circuit speed.

Abstract: Disclosed herein is a method that directs the components and signal detection path of a binary data bit decision mechanism used to obtain the bit error rate of the bit stream of an incoming or applied data signal to generate an eye diagram. More precisely, components such as the trigger-to-data delay adjustment to generate a delayed trigger pulse, the variable decision threshold setting, the bit detection flip flop in the input signal path to perform bit sampling, the total bits counter as a window size counter and the error counter to accumulate the occurrences when incoming signal exceeds a specified voltage threshold voltage range for a instance in time are used to implement the functionality required to generate the eye diagram.

Abstract: Variable phase bit sampling implementations are disclosed which minimize requirements for downstream digital processing resynchronization in systems that incorporate adjustable bit phase sampling that utilize variable delay elements which can interrupt the clocking stream signal. A sampling device includes a sampling circuit operative to provide an output signal in response to a data signal, where the sampling circuit includes a data input and a clock input. A variable delay circuit provides an adjustable trigger signal to the clock input in response to a first delay control signal. A fixed delay circuit delays the output signal by a predetermined amount of time in response to at least one delay control signal.

Abstract: A method and apparatus to draw eye diagrams of multi-valued signals that remove non-data dependent effects is disclosed. An exemplary method includes collecting event counts at variable bit offsets, desired time offsets within one or more bit periods and desired voltage offsets within a voltage region of interest; removing non-data dependent effects from the collected event counts; generating a composite diagram of the desired time offsets within the one or more bit periods of interest and desired voltage offsets within the voltage region of interest; and displaying the composite diagram.

Abstract: Apparatus and method for determining characteristics of a bit stream of binary pulses. The apparatus has control apparatus for defining a window comparator and logic apparatus for accumulating and mapping numbers derived from a count of the number of times the bit stream pulses fall at points inside the window comparator and drawing an eye diagram defining characteristics of the bit stream.

Abstract: A signal analysis circuit includes a sampling circuit operative to sample the characteristics of an input signal at various points within a bit window in response to a sample clock signal. A sampling control circuit is coupled to the sampling circuit and is operative to provide the sample clock signal in response to a sample control signal. The sample clock signal provides a variable time function such that the input signal characteristics may be sampled at several times during the input signal or bit window period. A control circuit is coupled to the sampling circuit and the sampling control circuit, and is operative to provide the sample control signal in response to the number of times the input signal is within a signal characteristic of interest. In an exemplary embodiment, the characteristic of interest is a reference pattern that may be synchronized with the input data signal.

Abstract: A measurement device includes a measurement circuit that generates a parametric measurement data signal including parametric characteristics of an input signal. In an exemplary embodiment, the parametric characteristics are measured at predetermined increments of time. A population limit analyzer is coupled to the measurement circuit and generates limit data in response to the parametric measurement data signal. A measurement limit checker is coupled to the population limit analyzer and generates a signal indicating that the characteristics of the parametric measurement data signal is within acceptable limits. With this information, the user is able to quickly grade a selected device under test (DUT). A device performance measurement method includes receiving an input signal. Next, statistical characteristics are determined from the parametric measurements of the input signal. Performance limits are extrapolated from the statistical characteristics of the parametric measurements.

Abstract: Disclosed herein is a method and apparatus used to create an idealized voltage controlled oscillator (VCO) which allows very high modulation rates without the expected phase noise (jitter) which nominally comes from wide bandwidth VCOs. In this fashion, high quality VCOs that typically offer pure signals at the cost of small tuning bandwidths can be enhanced to create idealized VCOs that offer both high quality (low jitter) and high tuning bandwidths. A high-frequency phase modulator and control voltage processing is used in conjunction with a natural VCO to create a method and apparatus in accordance with the invention. The control voltage processing includes separation of frequency components of the controlling voltage and electrical integration of high-frequency control voltage components directed to the phase modulator to create the overall voltage-to-frequency transfer function for the ideal VCO.

Abstract: Sub-sampled signals are compared to determine time delay, calibration of delay elements, and other precise time domain measurements, based on properties of aliased signals produced by the sub-sampling. In one embodiment, flip-flops sub-sample an input signal and a delayed signal. A counter measures time delay between edges in the sub-sampled input and sub-sampled delayed signal. The time delay is determined and averaged over a measurement window, and then scaled to determine an amount of delay of the delayed signal. Means to calibrate a delay element inside a measurement device (e.g., Bit Error Ratio Tester), utilizing sub-sampling techniques to achieve precise measurements very quickly and without the need for factory calibration.

Abstract: A differential signal reception device and method for supporting variable threshold levels. The device flexibly makes an input to the decision circuit appear to an outside driving circuit as if the decision circuit were a purpose-built input network supporting a fixed impedance input into either a floating or fixed DC termination voltage. The device further allows the internal decision process to support a variable threshold level when deciding logical 1/0 values and to attenuate the users input signal range for the purpose of making sure the range of the user's signals do not exceed the operating range of readily available decision circuit (limiting amplifier) integrated circuits.

Abstract: Disclosed herein is a method for determining the location of at least one error in a digital data stream and identifying the data surrounding the error which comprises selecting a user data stream to be analyzed for errors, selecting a seed bit segment out of the user data stream and converting that to a reference data stream, synchronizing the reference data stream with the user data stream, determining if an error exists, if an error has occurred calculating where on the data stream the error occurred, comparing the data stream segment containing the error with the reference data stream, analyzing the data surrounding the error, and computing actual data values from phase, data type and error location.

Abstract: The present invention relates to a differential signal reception device and method for supporting variable threshold levels. The present invention flexibly makes an input to the decision circuit appear to an outside driving circuit as if the decision circuit were a purpose-built input network supporting a fixed impedance input into either a floating or fixed DC termination voltag 1844X The present invention further allows the internal decision process to support a variable threshold level when deciding logical 1/0 values and to attenuate the users input signal range for the purpose of making sure the range of the user's signals do not exceed the operating range of readily available decision circuit (limiting amplifier) integrated circuits.

Abstract: Disclosed herein is a method and apparatus used to measure the number of time a multi-valued data signal transmitted from either a communication device of subsystem deviates across and into one or more bounded areas or zones as defined by an eye mask that is overlaid onto an eye diagram. The present invention employs an iterative process to accumulate and display mask violation that might result from a data signal transmitted from a target device or communications subsystem that deviates across the boundaries either above or below or into the center of the eye diagram. In addition, the present invention also has the ability to isolate particular threshold voltage-delay points along the boundaries above or below and around the perimeter of the mask polygon of the eye diagram where mask violations have occurred. This provides the ability to supply additional information and feedback about the behavior and performance of the targeted device or subsystem being tested.

Abstract: Disclosed herein is a method that directs the components and signal detection path of a binary data bit decision mechanism used to obtain the bit error rate of the bit stream of an incoming or applied data signal to generate an eye diagram. More precisely, components such as the trigger-to-data delay adjustment to generate a delayed trigger pulse, the variable decision threshold setting, the bit detection flip flop in the input signal path to perform bit sampling, the total bits counter as a window size counter and the error counter to accumulate the occurrences when incoming signal exceeds a specified voltage threshold voltage range for a instance in time are used to implement the functionality required to generate the eye diagram.

Abstract: Apparatus and method for determining characteristics of a bit stream of binary pulses. The apparatus has control apparatus for defining a window comparator and logic apparatus for accumulating and mapping numbers derived from a count of the number of times the bit stream pulses fall at points inside the window comparator and drawing an eye diagram defining characteristics of the bit stream.