Abstract: A host computer is coupled to a plurality of peripheral devices through a single parallel port in the host computer. A terminal adapter connected to the host computer parallel port includes a plurality of ports for connection to the plurality of peripheral devices. A host interface memory in the host computer receives control structures containing control and status information and data for peripheral device operation from device drivers in the host computer. The host interface memory buffers the control structures and a port interface operating through the host and terminal adapter parallel ports transports the control structures from the host computer to the terminal adapter. In the terminal adapter, a terminal adapter interface memory holds a mirror image of the contents of the host memory and the terminal interface accesses the terminal adapter interface memory to obtain control data structures which are used to operate the peripheral devices.