Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A multi-trench schottky diode includes a semiconductor base layer, a back metal layer, an epitaxial layer, an interlayer dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a termination trench structure, a first trench structure, a second trench structure and a third trench structure. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer stacked on the termination trench structure and the interlayer dielectric layer extends between the second trench structure and the third trench structure. The passivation layer is on the first metal layer and the interlayer dielectric layer. The second metal layer on the first metal layer and the passivation layer extends to the first trench structure. Thus, the electric field is dispersed and the voltage breakdown can be avoided with the trench structures in the termination area.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A Schottky diode with multiple guard ring structures includes a semiconductor base layer, a back metal layer, an epitaxial layer, a dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a terminal trench structure, a first ion implantation guard ring, a second ion implantation guard ring and a third ion implantation guard ring. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer is on the terminal trench structure and the dielectric layer. The passivation layer is on the first metal layer and the dielectric layer. The second metal layer is on the first metal layer and the passivation layer. Widths of the first, second and third ion implantation guard rings decrease in order, so that the voltage can be distributed step by step.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead frame has a die connection surface. The second lead frame is separated to the first lead frame. The second lead frame has a lead frame connection groove which defines a thermal deformation tolerance allowable route. The jumper structure is thermally deformed in a thermal-variable environment. The jumper structure includes a die welding portion and a lead welding portion. The die welding portion is welded to the die. Upon meeting a thermal deformation, the lead welding portion would be movable welded along the thermal deformation tolerance allowable route to the lead frame connection groove.

Abstract: A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead frame has a die connection surface. The second lead frame is separated to the first lead frame. The second lead frame has a lead frame connection groove which defines a thermal deformation tolerance allowable route. The jumper structure is thermally deformed in a thermal-variable environment. The jumper structure includes a die welding portion and a lead welding portion. The die welding portion is welded to the die. Upon meeting a thermal deformation, the lead welding portion would be movable welded along the thermal deformation tolerance allowable route to the lead frame connection groove.

Abstract: An integrated packaging structure is provided. In the package structure, an integrated component body has a first source region, a second source region, a first setting region, and a second setting region, which are separated from each other. A first MOSFET die and a second MOSFET die are located on the first setting region and the second setting region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed from the top surface and spaced apart from each other. A first source connection element is connected to the source electrode pad of the first MOSFET die and the first source region. A second source connection element is connected to the source electrode pad of the second MOSFET die and the second source region. A gate connection element is connected to the gate electrode pad and a gate region of the integrated component body.

Abstract: A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.

Abstract: A die-packaging component includes a substrate, a die, a jumper structure, a lead structure and a package body. The substrate has a base surface further including a die-connecting portion and a package-body retaining structure surrounding the die-connecting portion. The die connects the die-connecting portion. The jumper structure welded to the die generates a thermal deformation while in conducting a high-voltage current. The lead structure includes a lead groove defining a thermal-deformation tolerance allowable route. While in meeting the thermal deformation, the jumper structure welded to the lead groove as well is movable along the thermal-deformation tolerance allowable route. The package body at least partly covers the lead structure and the substrate, completely covers the die and the jumper structure, and is constrained by the package-body retaining structure.

Abstract: A switching mode constant current led driver including an energy transmission unit, an LED module, a power transistor, a resistor and a control unit, the control unit including a driving unit for generating a driving voltage signal, and a duty cycle determining unit for determining a duty cycle of the driving voltage signal, wherein, the duty cycle determining unit determines a charging time for a reference current to charge an external capacitor according to a present time length, and determines a discharging time for a discharging current to discharge the external capacitor according to an inductor discharging time, the discharging current being proportional to an average value of an inductor charging status signal, and a comparing voltage is thereby generated on the external capacitor; and compares the comparing voltage with a saw-tooth voltage to generate a next time length of the duty cycle.

Abstract: A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.

Abstract: A field effect transistor includes a substrate, an epitaxial layer, a remnant-oxide layer, an electrode, a surrounding-oxide layer, a surrounding-nitride layer, a gate oxide layer, a gate, a P-body region, a source region, an interlayer dielectric and a source electrode. The epitaxial layer on the substrate has a trench having a sidewall and a bottom. The electrode inside the trench is coated subsequently by the surrounding-oxide layer, the surrounding-nitride layer and the remnant-oxide layer. The gate formed on the gate oxide layer is separated from the electrode sequentially by the gate oxide layer, the surrounding-nitride layer and the surrounding-oxide layer. The P-body region and the source region, formed at the epitaxial layer, are separated from the gate by the gate oxide layer. The interlayer dielectric covers the source region and the gate. The source electrode covers the P-body region and the interlayer dielectric, and contacts the source region.

Abstract: A field effect transistor is manufactured by firstly forming an epitaxial layer on a substrate. Then, a trench having an oxide layer is formed on the epitaxial layer. The oxide layer has a first electrode portion having a first width and a first height and a second electrode portion having a second width and a second height. A gate oxide layer covering the oxide layer and the second electrode portion has a gate portion having a third width. The epitaxial layer has a body region and a source region, where these two regions are adjacent to the gate portion and covered by an interlayer dielectric. A source electrode covering the body region and the interlayer dielectric contacts the source region. The first height is no less than the second height, the first width is smaller than the second width, and the second width is smaller than the third width.

Abstract: A field effect transistor includes a substrate, an epitaxial layer, a remnant-oxide layer, an electrode, a surrounding-oxide layer, a surrounding-nitride layer, a gate oxide layer, a gate, a P-body region, a source region, an interlayer dielectric and a source electrode. The epitaxial layer on the substrate has a trench having a sidewall and a bottom. The electrode inside the trench is coated subsequently by the surrounding-oxide layer, the surrounding-nitride layer and the remnant-oxide layer. The gate formed on the gate oxide layer is separated from the electrode sequentially by the gate oxide layer, the surrounding-nitride layer and the surrounding-oxide layer. The P-body region and the source region, formed at the epitaxial layer, are separated from the gate by the gate oxide layer. The interlayer dielectric covers the source region and the gate. The source electrode covers the P-body region and the interlayer dielectric, and contacts the source region.