Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

Abstract: A regulator system includes a multi-bit detector system and a multi-cell charge/discharge circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of detectors has a predetermined threshold voltage. The multi-cell charge/discharge circuit includes a plurality of charge pumps. Each of the charge pumps is configured to generate a predetermined charge. Each of the charge pumps is associated with a predetermined threshold voltage of the detector circuit.

Abstract: A regulator system includes a multi-bit detector system and a multi-cell charge/discharge circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of detectors has a predetermined threshold voltage. The multi-cell charge/discharge circuit includes a plurality of charge pumps. Each of the charge pumps is configured to generate a predetermined charge. Each of the charge pumps is associated with a predetermined threshold voltage of the detector circuit.

Abstract: Methods of fabricating a semiconductor structure using a photoresist cross link process and a photoresist de-cross link process are described. A cross link bottom layer is employed during the fabricating process and the photoresist de-cross link process de-cross links the cross link bottom layer before the bottom layer is removed. The incorporation of the photoresist de-cross link process with the usage of the cross link bottom layer provides a cost effective and low defect level solution to fabricate the semiconductor structure.

Abstract: A regulator system includes a multi-bit detector system and a multi-cell charge/discharge circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of detectors has a predetermined threshold voltage. The multi-cell charge/discharge circuit includes a plurality of charge pumps. Each of the charge pumps is configured to generate a predetermined charge. Each of the charge pumps is associated with a predetermined threshold voltage of the detector circuit.

Abstract: A semiconductor package provides an IC chip on at least one package substrate and including signal bond pads, ground bond pads and power bond pads. The package substrate includes signal contact pads, ground contact pads and power contact pads which are respectively coupled to signal bond pads, ground bond pads and power bond pads formed on the IC chip. The contact pads are coupled to the associated bond pads by a bonding wire. The bonding wires that connect the power and ground pads have a thickness that is greater than the thickness of the bonding wires that couple the signal pads. The various bond pads on the IC chip may be staggered to provide for enhanced compactness and integration. The package substrates may be a plurality of stacked package substrates.

Abstract: A method and system is disclosed for reducing and monitoring precipitated defects on mask reticles. A predetermined gas is provided into an environment surrounding the reticle assembly for reducing a formation of the precipitated defects around the mask reticle caused by photolithography under a light source having a small wavelength.

Abstract: A polyimide processing tool for coating polyimide on a semiconductor wafer is provided with a pause time monitoring means for monitoring the duration of the polyimide processing tool's wafer-transfer robot's pause time. The wafer-transfer robot transfers wafers from polyimide apply tool to polyimide cure bake oven and monitoring the duration of the pause helps prevent undesirably long pauses between polyimide apply of the uncured polyimide and the curing step.

Abstract: The current generator circuitry for providing a reference current with small temperature dependence feature is disclosed. The circuitry comprises two PMOS transistors, two NMOS transistors, two diode, as well as two resistors. The first PMOS and NMOS transistors as well as the first diode are in series connected between a power reference and a potential reference. It flows with a primary current. The second PMOS transistor has a gate terminal connected to a gate of the first PMOS transistor thereto connect to a drain terminal of the second PMOS transistor. Furthermore, the second NMOS transistor has a gate terminal connected to a gate of the first NMOS transistor thereof connecting to a drain terminal of the first NMOS transistor. The second PMOS transistor, the second NMOS transistor, the second diode, the first resistor and the second resistor are in series connected between above power reference and the potential reference to flow a reference current.

Abstract: The device includes a N+ buried layer in a substrate. A P-well is formed in an epitaxial layer on the buried layer. N-wells surround the P-well are also formed in the epitaxial layer. One of the N-well regions acts as a drain in the structure. A plurality of field oxide regions is formed on the N-well or P-well to define the active area of the device. A gate oxide is formed on the surface of the P-well and the N-well served as the drain. A gate is formed on the gate oxide. Drain contact is formed in the N-well for drain. The source region of the device is formed in the P-well adjacent to the drain. An isolation layer is deposited on the gate. The method includes forming a N+ buried layer in a P substrate. A P epitaxial layer is then formed on the surface of the P substrate. The N-well and P-well are respectively formed in the epitaxial layer by ion implantation and thermally diffusion. A plurality of field oxide (FOX) regions are created to define the active area.