Patents Assigned to Taiwan Semiconductor Manufacturing Co., Ltd.
  • Three-dimensional memory device and method
    Patent number: 11985830
    Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Chung-Te Lin
  • Integrated circuit package and method
    Patent number: 11984372
    Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Yuan Lo, Lipu Kris Chuang, Hsin-Yu Pan
  • Dual silicide structure and methods thereof
    Patent number: 11984363
    Abstract: A semiconductor device includes a semiconductor substrate, a first epitaxial feature having a first semiconductor material over the semiconductor substrate, and a second epitaxial feature having a second semiconductor material over the semiconductor substrate. The second semiconductor material being different from the first semiconductor material. The semiconductor device further includes a first silicide layer on the first epitaxial feature, a second silicide layer on the second epitaxial feature, a metal layer on the first silicide layer, a first contact feature over the metal layer, and a second contact feature over the second silicide layer. A first number of layers between the first contact feature and the first epitaxial feature is greater than a second number of layers between the second contact feature and the second epitaxial feature.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Semiconductor package and method of forming same
    Patent number: 11984422
    Abstract: In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Hsien Huang, Yao-Chun Chuang, SyuFong Li, Ching-Pin Lin, Jun He
  • Glitch preventing input/output circuits
    Patent number: 11984883
    Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsin Yu, Nick Pai, Bo-Ting Chen
  • 3D memory array contact structures
    Patent number: 11985825
    Abstract: A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Feng-Cheng Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
  • Power distribution network
    Patent number: 11984443
    Abstract: An integrated circuit includes a first pair of power rails and a second pair of power rails that are disposed in a first layer, conductive lines disposed in a second layer above the first layer, and a first active area disposed in a third layer above the second layer. The first active area is arranged to overlap the first pair of power rails. The first active area is coupled to the first pair of power rails through a first line of the conductive lines and a first group of vias, and the first active area is coupled to the second pair of power rails through at least one second line of the conductive lines and a second group of vias different from the first group of vias.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kam-Tou Sio, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Semiconductor device and method
    Patent number: 11984402
    Abstract: In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Wang, Yu-Xuan Huang
  • Isolation structures of semiconductor devices
    Patent number: 11984476
    Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, I-Sheng Chen
  • SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS SHARING GATES WITH STRUCTURES HAVING REDUCED PARASITIC CIRCUIT
    Publication number: 20240153950
    Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng CHANG, Po-Lin PENG, Jam-Wem LEE
  • MULTI-BIT STRUCTURE
    Publication number: 20240153942
    Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 9, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Lun CHIEN, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
  • Semiconductor structure and method of forming the same
    Patent number: 11978676
    Abstract: A device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a dielectric fin over the substrate, a first isolation region between the first semiconductor fin and the dielectric fin, and a second isolation region between the first semiconductor fin and the second semiconductor fin. The first semiconductor fin is disposed between the second semiconductor fin and the dielectric fin. The first isolation region has a first concentration of an impurity. The second isolation region has a second concentration of the impurity. The second concentration is less than the first concentration. A top surface of the second isolation region is disposed closer to the substrate than a top surface of the first isolation region.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Ying Chen, Po-Kang Ho, Sen-Hong Syue, Huicheng Chang, Yee-Chia Yeo
  • Connection between source/drain and gate
    Patent number: 11980016
    Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Chia-Hao Pao, Yu-Kuan Lin, Lien-Jung Hung, Ping-Wei Wang, Shih-Hao Lin
  • Memory devices with gate all around transistors
    Patent number: 11980014
    Abstract: A memory structure and a system-on chip (SOC) device are provided. A memory structure according to the present disclosure includes a first static random access memory (SRAM) macro comprising first gate-all-around (GAA) transistors and a second SRAM macro comprising second GAA transistors. The first GAA transistors of the first SRAM macro each includes a first plurality of channel regions each having a first channel width (W1) and a first channel thickness (T1). The second GAA transistors of the second SRAM macro each comprises a second plurality of channel regions each having a second channel width (W2) and a second channel thickness (T2). W2/T2 is greater than W1/T1.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Semiconductor device with elongated pattern
    Patent number: 11978672
    Abstract: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact and a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The conductive via is over the source/drain contact. From a top view, the conductive via has two opposite long sides and two opposite short sides connecting the long sides, and the short sides are shorter than the long sides and more curved than the long sides.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chin Chang, Li-Te Lin, Pinyen Lin
  • Single bodied platen housing a detection module for CMP systems
    Patent number: 11975421
    Abstract: The present disclosure provides a chemical mechanical polishing system having a unitary platen. The platen includes one or more recesses within the platen to house various components for the polishing/planarization process. In one embodiment, the platen includes a first recess and a second recess. The first recess is located under the second recess. An end point detector is placed in the first recess and a detector cover may be placed in the second recess. A sealing mean is provided in a space between the end point detector and the detector cover to prevent any external or foreign materials from coming in contact with the end point detector. A fastener used for fastening the detector cover to the platen also provides addition protection to prevent foreign materials from coming in contact with components received in the recesses.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Lung Lai, Cheng-Ping Chen, Shih-Chung Chen, Sheng-Tai Peng, Rong-Long Hung
  • Semiconductor device and method for making the same
    Patent number: 11978782
    Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-? gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Yi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Semiconductor device with doped region between gate and drain
    Patent number: 11978797
    Abstract: A semiconductor device includes a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The doped region is in the drift region and between the drain region and the gate structure. From a top view the doped region has a strip pattern extending in parallel with a strip pattern of the gate structure.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 7, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Lian-Jie Li, Yan-Bin Lu, Feng Han, Shuai Zhang
  • Semiconductor device including a semiconductor fin comprising a silicon germanium portion and an isolation structure at a sidewall of the silicon germanium portion
    Patent number: 11978632
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a gate structure, and a source/drain feature. The semiconductor substrate includes a semiconductor fin, wherein the semiconductor fin comprises a silicon germanium portion. The isolation structure is at a sidewall of a bottom portion of the silicon germanium portion. A top portion of the silicon germanium portion is higher than a top surface of the isolation structure, and an atomic concentration of germanium in the top portion of the silicon germanium portion is greater than an atomic concentration of germanium in the bottom portion of the silicon germanium portion. The gate structure is over a first portion of the silicon germanium portion of the semiconductor fin. The source/drain feature is over a second portion of the silicon germanium portion of the semiconductor fin.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Cheng-Hsien Wu
  • Integrated circuit interconnect structure having discontinuous barrier layer and air gap
    Patent number: 11978663
    Abstract: A semiconductor structure includes a first dielectric layer, a first metallic feature over the first dielectric layer, an air gap over the first dielectric layer and adjacent to the first metallic feature, a second dielectric layer disposed above the air gap and on a sidewall of the first metallic feature, and a third dielectric layer disposed above the air gap and on a sidewall of the second dielectric layer. A lower portion of the first metallic feature is exposed in the air gap. The third and the second dielectric layers are substantially co-planar.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Lung Chung, Shin-Yi Yang, Ming-Han Lee