Abstract: A method and system is disclosed for inspecting defects on a wafer. After acquiring at least one digitized image of at least one portion of a wafer, at least one design database file corresponding to the portion of the wafer is converted into at least one inspection file. After setting one or more error detection thresholds, the digitized image and the inspection file are compared by an inspection tool for detecting defects with regard to the portion of the wafer based on the set error detection thresholds.

Abstract: A fabrication method for reducing the critical dimension of the conductive line and the space is described in which a conductive layer and a mask layer are sequentially formed on a substrate. A taper etching is conducted to form a plurality of first openings with the cross-sections of the openings being tapered off from top to bottom and exposing the surface of the conductive layer. A planarized sacrificial layer at a similar height as the mask layer is formed covering the exposed surface of the conductive layer. A second taper etching is further conducted on the exposed mask layer to form a plurality of second openings with the cross-sections of the openings being tapered off from top to bottom. The sacrificial layer is then removed. Thereafter, an anisotropic etching is conducted on the exposed conductive layer, using the mask layer as a hard mask, to form a plurality of conductive lines followed by a removal of the mask layer.

Abstract: A method is used to form a borderless via in a semiconductor device. A conductive layer, a borophosphosilicate glass (BPSG) layer and a patterned first mask layer are formed on a dielectric layer in sequence. The BPSG layer is patterned into a BPSG plug while using the patterned first mask layer as a mask. A second mask layer is formed to cover the patterned first mask layer and the metal layer. The conductive layer is defined to form a conductive line beneath the BPSG plug and the second mask layer. The first and second photoresist mask layers are removed. An inter-metal dielectric layer is formed around the BPSG plug and the conductive line. A via is formed in the inter-metal dielectric layer by removing the BPSG plug. A barrier layer and a metal layer fill the via to form a metal plug.

Abstract: A multi-level flash memory cell formed in a semiconductor substrate. The memory cell comprises: (a) a deep n-well formed in said semiconductor substrate; (b) a p-well formed within said deep n-well; (c) a first insulating layer formed over said p-well; (d) three floating gates adjacent to and insulated from one another and lying atop said first insulating layer; (e) source and drain regions formed in said p-well and on either side of said three floating gates; (f) a second insulating layer atop said three floating gates and said drain and source regions; and (g) a control gate formed atop said second insulating layer.

Abstract: A method of forming hemispherical grain (HSG) silicon is disclosed. The method comprises the steps of: forming a doped amorphous silicon layer on a substrate; seeding and annealing the amorphous silicon layer until HSG silicon is formed; enlarging the HSG silicon grains during the annealing stage; and performing a chemical dry etch on the HSG silicon to remove an undoped silicon layer from the surface of the HSG silicon.

Abstract: A method for forming a bottom storage node of a capacitor for a DRAM memory cell on a substrate is disclosed.

Abstract: A method of forming an ETOX-cell in a semiconductor substrate is disclosed. The method begins with forming a p-well in the substrate. Then, a drain region and a source region is formed in the p-well. The drain region is of a first dopant type and the source region is of a second dopant type (i.e. same as the dopant type of the p-well). A floating-gate and tunnel oxide stack is formed above the p-well, the floating gate formed between the drain region and the source region and only after the drain region and the source region have been formed. The floating gate is doped with the same dopant type as the p-well. Finally, a control gate is formed above the floating-gate, the floating-gate and the control gate separated by a dielectric layer. The new ETOX cells can be organized into a NOR array, but with no need of source line connections. Each cell is programmed by band-to-band induced substrate hot-electron (BBISHE) at the source, and read by GIDL at the drain side.

Abstract: An inverter formed in a semiconductor substrate is disclosed. The inverter comprises: a p-well formed in the substrate, the p-well being the output of the inverter; a gate structure formed atop the p-well, the gate structure being the input of the inverter and being formed from a thin gate oxide layer underneath a conductive layer; an n- base formed adjacent to a first edge of the gate structure; a p+ structure formed within the n- base; and a n+ structure adjacent a second edge of the gate structure.

Abstract: This invention provides a method of preventing contact autodoping and supressing tungsten silicide peeling during the reflow cycle for a borophosphosilicate glass insulating layer during fabrication of large scale integrated circuits. The invention uses a thin oxide layer to protect the contact areas during the reflow cycle. The thin oxide layer is thin enough to allow satisfactory reflow of the borophosphosilicate glass insulating layer and thick enough to prevent autodoping and tungsten silicide peeling. The thin oxide layer is also thin enough so that process time required to remove the thin oxide layer is not a significant increase in process time. The thin oxide layer thickness is controlled by depositing a helium diluted tetraethoxysilane vapor and oxygen using chemical vapor deposition.

Abstract: A new method of simultaneously forming differential gate oxide for both 3 and 5 V transistors is described. A sacrificial silicon oxide layer is formed on the surface of a semiconductor substrate. Ions are implanted through the sacrificial silicon oxide layer into the planned 3 V transistor area of the semiconductor substrate wherein the implanted ions depress the oxidation rate of the semiconductor substrate. Alternatively, ions are implanted through the sacrificial silicon oxide layer into the planned 5 V transistor area of the semiconductor substrate wherein the implanted ions increase the oxidation rate of the semiconductor substrate. The sacrificial silicon oxide layer is removed and a layer of gate silicon oxide is grown on the surface of the semiconductor substrate.