Abstract: A method includes forming a first isolation region in a substrate, wherein a top surface of the first isolation region is lower than a top surface of the substrate, depositing a gate electrode layer over the substrate and patterning the gate electrode layer to form a first gate electrode region and a second gate electrode region, wherein the second gate electrode region is vertically aligned with the first isolation region and the first gate electrode region is immediately adjacent to the second gate electrode region.

Abstract: A sense amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistive device, a second resistive device, a fifth transistor and a sixth transistor. A gate of the first transistor is coupled to a drain of the fourth transistor. A drain of the first transistor is coupled to a gate of the fourth transistor. A gate of the second transistor is coupled to a drain of the third transistor. A drain of the second transistor is coupled to a gate of the third transistor. The first resistive device is coupled to a first data line and at least the drain of the first transistor or third transistor. The second resistive device is coupled to a second data line and at least the drain of the second transistor or the fourth transistor. The sources of the third and fourth transistor are coupled together.

Abstract: A wafer chuck is cleaned using a cleaning cap to remove processing residue and particulate matter. The cleaning cap is configured to overlie and align with the wafer chuck and includes a base and a first roller connected to the base and having wound therearound a cleaning cloth. The cleaning cap further includes a second roller connected to the base and having attached thereto a free end of the cleaning cloth. During use, the cleaning cloth winds upon the second roller from the first roller when the second roller rotates about its axis. The cleaning cap can be positioned relative the wafer chuck by way of a manipulator to ensure the cleaning cloth contacts the wafer chuck with sufficient force. The cleaning cloth rubs the wafer chuck with both translational motion and rotational motion.

Abstract: The present disclosure provides for various advantageous methods and apparatus of controlling electron emission. One of the broader forms of the present disclosure involves an electron emission element, comprising an electron emitter including an electron emission region disposed between a gate electrode and a cathode electrode. An anode is disposed above the electron emission region, and a voltage set is disposed above the anode. A first voltage applied between the gate electrode and the cathode electrode controls a quantity of electrons generated from the electron emission region. A second voltage applied to the anode extracts generated electrons. A third voltage applied to the voltage set controls a direction of electrons extracted through the anode.

Abstract: A semiconductor processing station is provided. The semiconductor processing station includes a first platform, a second platform and a vacuum tunnel, wherein the first platform has a first load lock and a first plurality of chambers, and the second platform has a second load lock and a second plurality of chambers, and the vacuum tunnel connects the first and the second load locks.

Abstract: A Micro-Electro-Mechanical System (MEMS) device includes a sensing element, and a proof mass over and overlapping at least a portion of the sensing element. The proof mass is configured to be movable toward the sensing element. A protection region is formed between the sensing element and the proof mass. The protection region overlaps a first portion of the sensing element, and does not overlap a second portion of the sensing element, wherein the first and the second portions overlap the proof mass.

Abstract: An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.