Abstract: Semiconductor device junction simulation is carried out utilizing models that are developed with series resistance extractions that improve their fidelity particularly in the high current regions of device operation. The models may also be tailored to account for geometric considerations of the semiconductor devices thereby allowing for a more flexible model and simulation by providing for geometric scaling capabilities.

Abstract: A composite shadow ring that is constructed of an upper ring and a lower ring assembled together by a plurality of dowel pins and a method for using the ring. The upper ring and the lower ring each has a predetermined outside diameter that is substantially the same, a planar top surface and a planer bottom surface parallel to the planar top surface. Each of the planar bottom surface of the upper ring and the planar top surface of the lower ring has at least two blind holes formed therein. A plurality of dowel pins are used to frictionally engage the at least two blind holes in the upper ring and the at least two blind holes in the lower ring.

Abstract: A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.

Abstract: A method of accounting for manufacturing resource re-entry constraints in a manufacturing planning system includes: building a relationship from a manufacturing operation to be rendered on lots of material, to a plurality of manufacturing resources capable of performing the operation, wherein at least one of the manufacturing resources is also capable of performing the operation on ones of the lots having manufacturing resource re-entry constraints; selecting one of the lots of material; selecting from any of the plurality of manufacturing resources in the relationship a manufacturing resource for performing the operation if the selected lot of material has no manufacturing resource re-entry constraints; and selecting from any of the at least one manufacturing resources in the relationship a manufacturing resource for performing the operation if the selected lot of material has manufacturing resource re-entry constraints.

Abstract: An algorithm can be performed to control the dispatch of products in a fabrication or manufacturing facility. The queue time constraint tolerances and tool throughput are initialized for each product. Next the multiple processing demand time can be calculated for each product. The aggregating queue time constraint can then be calculated for each product. If the multiple processing demand time is less than the aggregating queue time constraint for each queue time limit tool, then any lot can be selected to be processed. Otherwise, the product at the given tool should be further processed.

Abstract: A method for forming a low voltage coefficient capacitor. A doped polysilicon layer is formed in a region predetermined to form a capacitor and a doped polysilicon layer is formed in a region predetermined to form a gate. A silicide layer is formed on the doped polysilicon layer serving as a bottom electrode of a capacitor.

Abstract: A method for fabricating a shallow trench isolation structure. A pad oxide layer and a pad silicon nitride layer are formed over a substrate and are patterned to form a trench in the substrate. A high-density plasma (HDP) oxide layer is formed to fill the trench of a certain thickness. A silicon nitride layer is formed over the substrate. The silicon nitride layer and the oxide layer together form a protruding portion. A chemical-mechanical polishing is performed in a range of from at least removing the protruding portion to exposing the silicon nitride layer. The HDP oxide layer is etched until the HDP oxide layer on the pad silicon nitride layer is removed. The pad silicon nitride layer and the silicon nitride layer are removed by etching.

Abstract: A method of manufacturing a DRAM capacitor is described. A silicon substrate structure includes an oxide layer over a substrate and a polysilicon layer over the oxide layer. The polysilicon layer also includes a plug that penetrates the oxide layer. A patterned photoresist layer is next formed over the polysilicon layer. Spacers having a low etching rate are formed on the sidewalls of the photoresist layer by carrying out a chemical reaction next to the sidewall of the photoresist layer. A dry etching operation is carried out to etch the unreacted photoresist layer and the polysilicon layer exposed by the openings in the photoresist layer. Using the spacers as an etching mask, a portion of the polysilicon layer under the photoresist layer is removed by continuing the dry etching operation. Lastly, the spacers are removed to form a crown-shaped capacitor.

Abstract: A method for manufacturing a metal plug. The method includes the steps of providing a substrate having an insulation layer thereon, and then forming an opening in the insulation layer. Next, a conformal barrier layer is formed over the insulation layer and the sidewalls of the opening, and then metal is deposited to fill the opening and cover the barrier layer. Thereafter, the metallic layer above the barrier layer is etched back so that a metal plug is formed inside the opening. Finally, a chemical-mechanical polishing operation is carried out using the insulation layer as a polishing stop. A low polishing speed is used in the polishing operation so that a highly planar metal plug surface is obtained.

Abstract: A method of manufacturing a deep trench capacitor. A first silicon oxide layer is formed on a substrate. A first trench is formed in the substrate. A rugged polysilicon layer is formed on the surface of the first trench. The grains of the rugged polysilicon layer are distributed discretely on surface of the first trench. A second silicon oxide layer is formed on the rugged polysilicon layer. The exposed substrate in the first trench is etched, in order to form a plurality of second trenches in the substrate of the first trench. The first and second silicon oxide layer are removed. A first conductive layer is formed over the substrate and conformal to the first trench and the second trenches. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer.

Abstract: A method for fabricating the floating gate of a split-gate flash memory. A patterned sacrificial layer is formed over a substrate. A doped polysilicon layer and an insulation layer are formed in sequence over the sacrificial layer. The doped polysilicon layer and the insulation layer above the sacrificial layer are removed by chemical-mechanical polishing. The exposed doped polysilicon layer is removed. Finally, the sacrificial layer is removed to complete the fabrication of the floating gate.

Abstract: A flash memory with a split gate. The flash memory is formed on a semiconductor substrate, comprising a channel region, a tunnel oxide layer, a floating gate, a control gate, a dielectric layer and two source/drain regions. The channel region is located on a surface of the semiconductor substrate and partly covered by the floating gate. The floating gate is funnelform, that is, having a gradually diffusing cross sectional profile from a bottom surface to a top surface, and has a tunnel oxide layer to isolate with the semiconductor substrate, and there is an annulus tip on the rim of the top surface. The dielectric layer is located on a part of the top surface and a sidewall of the floating gate and a part of the channel region uncovered by the floating gate. The control gate is formed on the dielectric layer, and the source/drain regions are formed in the semiconductor at both sides of the channel region.