Abstract: Magazines, each loaded in series with IC elements to be tested, are stacked and such stacked magazines are arranged in columns. The lowermost magazines of the stacked magazines of the respective columns are simultaneously brought down by a takeout mechanism onto a magazine receiver, and the magazines on the magazine receiver are simultaneously but intermittently fed by intermittent stepping means in the direction of their arrangement. The outermost one of the magazines on the magazine receiver is loaded at an IC element receiving position. The IC elements from the magazine are supplied to a testing station, wherein they are tested, and the tested IC elements are sorted in a sorting station according to their test results and respectively then loaded into IC element receiving magazines in an accumulating station. The accumulating station has an IC receiving magazine stocker room in which IC element receiving magazines are stacked, and an empty magazine stocker room in which empty magazines are stacked.

Abstract: Magazines, each loaded in series with IC elements to be tested, are stacked and such stacked magazines are arranged in columns. The lowermost magazines of the stacked magazines of the respective columns are simultaneously brought down by a takeout mechanism onto a magazine receiver, and the magazines on the magazine receiver are simultaneously but intermittently fed by intermittent stepping means in the direction of their arrangement. The outermost one of the magazines on the magzine receiver is loaded at an IC element receiving position. The IC elements from the magazine are supplied to a testing station, wherein they are tested, and the tested IC elements are sorted in a sorting station according to their test results and respectively then loaded into IC element receiving magazines in an accumulating station. The accumulating station has an IC receiving magazine stocker room in which IC element receiving magazines are stacked, and an empty magazine stocker room in which empty magazines are stacked.

Abstract: An IC element supplied to a testing station is guided by a rail and a guide member to move by its own weight. At least one of the rail and guide member has built therein plate-shaped ceramic heater or plate-shaped silicone rubber heater. The guide member urges the IC element against the rail to heat the IC element. An auxiliary stopper is provided opposite but aslant to the IC element sliding surface of the rail. The IC element moving on the rail is yieldingly urged by the auxiliary stopper against the sliding surface of the rail, braked and engages an engaging piece at the lower end of the auxiliary stopper. The IC element is disengaged from the engaging piece to slightly move and stopped by a main stopper, where the IC element is tested. A plurality of such testing passages are provided, and IC elements simultaneously tested in the testing passage are fed to discharge rails respectively corresponding thereto.

Abstract: A signal detector identifies a desired frequency component having the greatest amplitude in an input signal containing other frequency components of smaller amplitude such as spurious noise, etc. This allows measuring for instance the frequency of the desired frequency component. The envelope of an intermediate frequency signal corresponding to the desired frequency component is set to be above a desired level in a single sweep of a local oscillator by comparing the envelope with a predetermined value for controlling the attenuation of the input signal. After the attenuation is thusly set, only the desired frequency component has an envelope larger than the predetermined value, so that the desired frequency component is easily identified thereby in the next sweep.

Abstract: A test pattern generator includes means for reading out a plurality of memories non-successively while outputting the test patterns stored identically in the addresses of the memories, such as for sequentially repeating the test patterns that are provided to a logic circuit being tested. The sequence of test patterns is determined by a series of instructions which are accessed by a program counter, and the instructions can cause a jump in the counting of the program counter, for instance to repeat addresses of the memories for repeating a desired sequence of test patterns a predetermined number of times. The timing of the addressing of the memories for the reading out of the test patterns can be faster than the timing for writing the test patterns into the memories for storage.

Abstract: A test pattern generator for providing test patterns to a logic circuit under test, wherein the logic circuit to be tested does not have a terminal for being set to an initial state before starting the test patterns. The initial state of the logic circuit is detected while supplying an increment pattern to increment the internal state, and the test patterns are supplied a predetermined number of clock pulses after the initial state is detected. The length of the period of the clock pulses for the test can be varied.

Abstract: A test system for simultaneously testing a plurality of logic circuits first sets them all to an initial state before beginning testing. The faulty logic circuits which cannot be set to the initial state can be identified, and the testing of the others can proceed, even after only one cycle of attempting to initialize all the logic circuits. If all the logic circuits are faulty, the further testing can be prevented.

Abstract: A multi-slope analog-to-digital converter avoids the dielectric absorption problem by providing a predetermined number of risings and fallings of the output of an integrator integrating an input analog signal during a first predetermined period of time, each falling corresponding to the simultaneous integration of a first reference signal during the first integration period. Subsequently the first reference signal is integrated for a time period to assure that the output signal of the integrator has a predetermined polarity, prior to completing the measurement of the input analog signal during further integration periods. Variations in the number of switching delays, and variations depending upon the direction with which the output of the integrator approaches a reference level, may thus be avoided.

Abstract: A central processing unit is cascade-connected with a plurality of I/O units, and a bus interconnecting them comprises a plurality of data lines for transmitting a control command signal, an address signal and a data signal on a time shared basis, a plurality of tag lines, each transmitting a tag signal indicating which one of the signals is provided on the data lines, and a clock line for transmitting a clock signal for these signals.

Abstract: A method for compensating for errors in reference current ratios in a multi-slope A-D converter allows determining multiplying factors for correcting the measured digital values of input analog signals that are being measured. The multiplying factors are determined using the components of the A-D converter.

Abstract: A word of a test pattern is divided into blocks and stored in a storage device of a test pattern generator for testing a logic device. The test pattern blocks are sequentially provided to respective blocks of a pattern generator, which provides at respective outputs all of the blocks of a test pattern word at the same time. If a block of the pattern generator is faulty, or if another component of the test pattern generator corresponding to a block of the pattern generator is faulty, the respective block of each test pattern word can be provided to an unused block of the pattern generator, for providing the test patterns for testing the logic device without the need for reprogramming the test pattern blocks to be stored in the storage device. The data stored in the storage device identifies the position of each respective block of the test pattern words, for controlling the transferring of the test pattern blocks from the storage device to the pattern generator.

Abstract: A counter counts clock signals following a reference signal to provide an address for accessing a memory wherein marks are stored at respective addresses corresponding to desired timing signals with respect to the reference signal. The memory has plural channels, all of which are accessed by the same count value, to provide different timing signals on different channel outputs corresponding to the marks stored in respective portions of the memory. Different sets of timing signals can be stored in different memory blocks, and the memory block which is accessed by the count value can be selected. The memory can be divided into plural memories of smaller capacity, and low speed memories can be used. A timing signal with respect to a first reference signal can be provided after the occurrence of the subsequent reference signal.

Abstract: A device for determining with high accuracy the period and frequency of an input signal by taking into account the fractions of a clock signal that are normally ignored. A gate signal with an integral number of clock pulses is generated. Each fractional time is accurately measured by first and second integrators, and an up-down counter provides the difference between the fractional times for the final determination.

Abstract: A signal generator generates a test signal for input to a device under test the output signal of which is subjected to fast Fourier transform analysis by a fast Fourier transformer. A waveform memory is read out in synchronism with data input to the fast Fourier transformer. The waveform memory has stored therein sample values of a composite waveform of a plurality of predetermined spectra. The output read out from the waveform memory is converted by a D/A converter into an analog signal for use as the test signal.

Abstract: An interval-expanding timer compensated for drift and nonlinearity in which a time interval .DELTA.T+nT.sub.0 of the sum of a time interval .DELTA.T to be measured and a constant time interval nT.sub.0 and time intervals (n+1)T.sub.0 and nT.sub.0 are respectively measured after being expanded and the expression ##EQU1## is calculated based on the measured results, thereby to measure the time interval .DELTA.T. The expansion of the time intervals is carried out in the following manner: A fixed voltage is integrated by a first integrator for a given period of time, and the fixed voltage is integrated by a second integrator at an integration rate smaller than that of the first integrator. Coincidence is detected between the integrated outputs from the first and second integrators, and the time interval from the start of integration by the second integrator to the detection of coincidence is provided as the interval-expanded output. The time intervals .DELTA.T+nT.sub.0, (n+1)T.sub.0 and nT.sub.

Abstract: An IC tester has a plurality of drivers for delivering test pattern signals through connector lines to corresponding terminal pins of an IC being tested. Outputs supplied from the IC being tested in response to the test pattern signals are delivered back through the connector lines to comparators coupled with output terminals of the drivers, respectively, so that the outputs from the IC can be determined as to their logic levels by the comparators. A plurality of low-pass filters are connected in series between the drivers and junctions between the comparators and the connector lines. Each of the low-pass filters has a ground terminal connected to ground through a switch which is controlled to be turned off at least when an output is supplied from the IC being tested. The low-pass filter has a cutoff frequency selected so that the test pattern signals will have desired rise and fall characteristics.

Abstract: A sweep voltage from a sweep voltage generator is provided to sweep start and stop adjusting means, the outputs of which are summed by a summing circuit and, by the summed output, the oscillation frequency of a voltage controller oscillator is controlled. The oscillation frequency of the voltage controlled oscillator and the output frequency of a reference signal generator set to a sweep start frequency are compared by comparing means. The output of the sweep voltage generator is put in a sweep start state and sweep start adjusting means is adjusted in accordance with the output of the comparing means, thereby to cause the oscillation frequency of the voltage controlled oscillator to agree with a set sweep start frequency. The output of the sweep voltage generator is put in a sweep stop state and sweep stop adjusting means is adjusted in accordance with the output of the comparing means, thereby to cause the oscillation frequency of the voltage controlled oscillator to agree with a set sweep stop frequency.

Abstract: A delay signal generating circuit includes feedback loops and components for selectively setting the delay time of a delay unit in one of the loops. The circuit can be used to provide an adjustable delay to a signal being propagated therethrough, and the delay unit can be bypassed.

Abstract: An IC tester supplies test pattern signal to an IC being tested and compares response signals therefrom with an expected-value pattern signal to determine whether the IC is acceptable or not. During the test, the IC being tested is severed by a separator means from the drivers, for producing the test pattern signals with a timing signal generator set in a condition for generating reference signals. The reference signals and the outputs from the drivers are compared for phase by a phase comparator means. Variable delay means inserted in the paths of the test pattern signal are adjusted by the result of the comparison to suppress skews between the paths of the test pattern signals. Skews in strobe signals, which serve to determine the logic levels of the response signals output from the IC being tested, are also suppressed.

Abstract: The output from a first variable frequency oscillator is frequency divided by a variable frequency divider and the frequency-divided output is phase compared by a first phase comparator with a first reference signal. By the phase-compared output is controlled a second variable-frequency oscillator of higher frequency stability than that of the first variable frequency oscillator. The output from the first variable oscillator is frequency divided by another frequency divider and the frequency-divided output is phase compared by a second phase comparator on the basis of the output from the second variable frequency oscillator and, by the phase-compared output, the first variable frequency oscillator is controlled. By changing the frequency dividing ratio of the variable frequency divider, the oscillation frequency of the first variable frequency oscillator is set.