Abstract: An apparatus and method, using an inter-processor lock to coordinate signal delivery to a process group whose member processes are distributed across multiple processors. The apparatus and method insure that each process group member process receives the same signals in the same order and that no signal is duplicated. The apparatus and method also insure that a partially completed signal delivery is completed even in the face of failure of the signalling processor.

Abstract: The present invention is a distributed computer system having a plurality of end user terminals and a plurality of loosely coupled server computers that share no resources with each other. A multiplicity of user application processes are distributed over the server computers. A transaction start table, stored on a first one of the server computers, stores transaction start data representing transactions whose execution has been requested by other transactions being executed by the user application processes. The transaction start data indicates a start condition for each transaction whose execution has been requested. For most requested transactions the start condition is a time value indicating an earliest time at which the requested transaction's execution should be started. When any of the user application processes executes a Start transaction function, a transaction start record is generated and stored in the transaction start table.

Abstract: A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

Abstract: A database computer system includes memory, residing in a plurality of interconnected computer nodes, for storing database tables. Each database table has a plurality of columns, a primary key index based on a specified subset of the columns, and an associated table schema. At least a subset of the database tables are partitioned into a plurality of partitions, each partition storing records having primary key values in a primary key range distinct from the other partitions. A transaction manager generates and stores an audit trail, each audit entry denoting a database table record event, such as an addition, deletion or alteration of a specified database table record in a specified one of said database tables. Four online data definition procedures allow the structure of a database table to be altered while the database table remains available to execution of transactions, with minimal impact of the availability of the database table for transaction execution.

Abstract: A system and method for automatically checkpointing a primary computer process to a backup computer process is disclosed. The system and method automatically convert a non-fault tolerant computer program into a fault tolerant computer program. The system includes multiple CPUs, a communications link between the CPUs and a user interface device, such as a terminal, workstation, or PC. A special layer of code forms an interface between the operating system for each CPU and the application programs running on the CPUs. For each process, running on one of the CPUs, the interface automatically creates a duplicate backup process on another CPU. The interface handles synchronizing communications between the original or primary process and the backup process, and suppresses or otherwise prevents or inhibits output from the backup process.

Abstract: A system providing a multiple number of virtual channels in a computer system having a smaller number of physical channels. Multiple queues are provided that are mapped to channels. The mapping of the queues to the channels changes depending on the message traffic and priority of the queues. Queues of lower priority are preempted if a higher priority queue needs a channel.

Abstract: In a computer system, data records stored in nonvolatile memory are read into a volatile memory and operated on in a sorting operation. A tournament-type sort is applied, with the tree size dynamically reconfigured within the volatile memory as a function of the number of data records to be sorted. The memory space occupied is reduced by the reconfigured tree and sort speed is augmented.

Abstract: Apparatus for cooling a plurality of electrical components mounted to a circuit board includes a base plate mounted in proximate relation to component sites on the circuit board at which electrical components are mounted. The base plate includes alignment elements that engage a alignment plate. The electrical components are carried by the alignment plate so that when the alignment plate is installed on the base plate, engaging the alignment elements, the electrical components are registered to and installed at corresponding component sites in a manner that aligns electrical leads of the components to printed circuit pads at the component sites. The base plate and alignment plate are sealed, and a coolant circulated therethrough.

Abstract: An apparatus and method for testing objects in an object-oriented programming environment. The object class hierarchy is defined so that a TopObject has a constructor function that initializes a linked list when the first class in the hierarchy is instantiated to create the first object. Each time an object of a class in the TopObject class hierarchy is instantiated, the TopObject constructor adds an entry for the new object to the linked list. A TestObject accesses the list to perform a predetermined testing function on one or more of the objects in the system. The object hierarchy class can also be defined as having multiple inheritance such that a class in the program inherits program functionality from one class and inherits testing functionality from the test class.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A fault tolerant computer system distributes audit trail files containing audit records, across an arbitrary number of disk volumes. After one audit trail file becomes full, audit records are directed toward a next audit trail file stored on a different disk volume. Storage of newly generated audit rotates through the disk volumes in round-robin fashion. Full audit trail files are eventually archived and their space becomes available again for renaming and storage of newly generated audit records. The number of audit records available for on-line recovery after a failure is not limited to the storage capacity of any single disk volume. Furthermore, there is no contention for disk access between archiving of full audit trail files and storage of newly generated audit records.

Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

Abstract: A digital control circuit is constructed to use a single signal line for the dual functions of control and sensing the presence of the controlled device. The control circuit includes a driver element having an output capable of being placed in a high impedance allowing the signal line to be pulled to a first predetermined voltage potential when the controlled device is connected thereto, and a second voltage potential when the controlled device is absent therefrom. A receiver circuit monitors the signal line to sense presence of the one or the other of the voltage potentials.

Abstract: A multiple processor system includes at least one process pair each including a plurality of modules. The modules perform functions related to multiple independent threads, and are arranged in a predetermined order such that higher modules are dependent upon lower modules, and lower modules are independent from higher modules. Each process pair is initially unaware of the number and order of the modules. The order of the modules is related to dependency and interdependency between the modules so that there is a portion of higher modules and a portion of lower modules. Multiple independent threads process the modules to cause activities in the portions of higher modules to take place before activities in the portions of lower modules.

Abstract: An apparatus and method, using an inter-processor lock to control access to inter-process relationship data structures in the memory of each processor in a multiprocessor system. The apparatus and method insure that each inter-process relationship is modified in the same sequence on each processor. The apparatus and method also insure that an inter-process relationship is maintained in a consistent state in the face of failure of any of the processors.

Abstract: An improved network timer for use in a network node, preferably a reliable mode network employing IPX/SPX data packets on workstations or computer. A method and apparatus is disclosed for use by a workstation node whereby a plurality of data packet timers may be supported and set, triggered and deleted in a maximum of K operations or time increments, where K is a constant and not a function of N.

Abstract: A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

Abstract: Two identical streams of multi-bit symbols are received by a pair of storage elements, each having multiple locations and first and second pointer counters respectively identifying the locations at which received symbols are stored and from which stored symbols are retrieved. The storage elements are synchronized by providing each with a SYNC symbol that, when detected, causes the pointer counters to be placed in a predetermined (reset) state on one transition of a SYNC clock signal, releasing the pointer counters at the same time on a following transition of the SYNC clock signal.

Abstract: A computer architecture has a plurality of processing cells interconnected to perform programming tasks. Each cell contains both memory and processing elements. Memory packets contain an instruction, a data element, and a pointer to another memory packet. Tasks are executed by following a linked list of memory packets. Transmission packets communicate instructions and register values along the linked list. A plurality of computer processes may be executed simultaneously.

Abstract: Link Ids are associated with file handles in a directory structure in a computer operating system. The Link Ids allow a file handle to be mapped uniquely to a pathname for a file associated with the file handle. In one implementation lists are used to facilitate fast searching of directory structures for a name associated with a Link Id. The list includes entry pairs where each entry pair is a Link Id and a directory number where a name associated with the Link Id may be found.