Patents Assigned to Tanisys Technology, Inc.
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Patent number: 9626264Abstract: Disclosed herein are a method and an apparatus for shortening a data comparison test time by using peer-to-peer transfers between peripheral component interconnect express (PCIe) endpoints when testing solid state drive (SSD) devices. A memory device test apparatus performing a data comparison test of a memory device mounted in a downstream port of a peripheral component interconnect express (PCIe) switch by performing a writing process and a reading-back process by a control of a host central processing unit (CPU) includes: a comparison test unit (FPGA) connected to the downstream port of the PCIe switch, performing peer-to-peer communication with the memory device to supply write data to the memory device and receive read-back data from the memory device, and performing the data comparison test.Type: GrantFiled: March 18, 2015Date of Patent: April 18, 2017Assignees: Neosem Inc., Tanisys Technology, Inc.Inventors: Dong Hyun Yeom, Bruce A. Parker
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Patent number: 6892328Abstract: A distributed tester method and system communicates test recipes for testing electronic devices from a host computer over a network to a test site. The test site translates test recipes into test instructions for execution by a test engine that determines the status of the electronic device. For instance, in a tester for testing memory, a test recipe is defined and stored with a host computer to determine test data for storage on the memory device under test at the test site. The host computer controls execution of the test recipe over the network. The test recipe is defined and stored in an XML formatted data file transmitted over the network to a processor at the test site. The test site processor translates the XML formatted data into test instructions for execution by a test engine. The test engine determines whether the memory device under test accurately stores data and provides the results, such as erroneously stored data, to the host computer through the network.Type: GrantFiled: September 27, 2001Date of Patent: May 10, 2005Assignee: Tanisys Technology, Inc.Inventors: Joseph C. Klein, Jack C. Little, Paul R. Hunter, Archer R. Lawrence
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Patent number: 6480799Abstract: A system and method for testing a RIMM loaded with RDRAM integrated circuits generates and reads test transaction data with a test transaction engine, such as a microprocessor-based memory tester. A RIMM adapter interfaces with the test transaction engine and the RIMM under test to communicate test data, including test write, address, control and read data. A comparison of test read data returned to the test transaction engine from the RIMM against predetermined values allows a determination of the operational status of the RIMM. The RIMM adapter is embodied as an ASIC with plural FIFO circuits interfaced between the test transaction engine and a channel controller and RAC. The FIFOs reconcile differences in timing between generation and return of test data and demands by the RAC and channel controller. Separate read and write data paths between the test transaction engine and ASIC support improved rates of data transfer.Type: GrantFiled: August 31, 2001Date of Patent: November 12, 2002Assignee: Tanisys Technology, Inc.Inventor: Paul R. Hunter
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Publication number: 20020042897Abstract: A distributed tester method and system communicates test recipes for testing electronic devices from a host computer over a network to a test site. The test site translates test recipes into test instructions for execution by a test engine that determines the status of the electronic device. For instance, in a tester for testing memory, a test recipe is defined and stored with a host computer to determine test data for storage on the memory device under test at the test site. The host computer controls execution of the test recipe over the network. The test recipe is defined and stored in an XML formatted data file transmitted over the network to a processor at the test site. The test site processor translates the XML formatted data into test instructions for execution by a test engine. The test engine determines whether the memory device under test accurately stores data and provides the results, such as erroneously stored data, to the host computer through the network.Type: ApplicationFiled: September 27, 2001Publication date: April 11, 2002Applicant: Tanisys Technology Inc.Inventors: Joseph C. Klein, Jack C. Little, Paul R. Hunter, Archer R. Lawrence
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Patent number: 6285962Abstract: A system and method for testing a RIMM loaded with RDRAM integrated circuits generates and reads test transaction data with a test transaction engine, such as a microprocessor-based memory tester. A RIMM adapter interfaces with the test transaction engine and the RIMM under test to communicate test data, including test write, address, control and read data. A comparison of test read data returned to the test transaction engine from the RIMM against predetermined values allows a determination of the operational status of the RIMM. The RIMM adapter is embodied as an ASIC with plural FIFO circuits interfaced between the test transaction engine and a channel controller and RAC. The FIFOs reconcile differences in timing between generation and return of test data and demands by the RAC and channel controller. Separate read and write data paths between the test transaction engine and ASIC support improved rates of data transfer.Type: GrantFiled: March 15, 1999Date of Patent: September 4, 2001Assignee: Tanisys Technology, Inc.Inventor: Paul R. Hunter
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Patent number: 6182253Abstract: A time conserving method of identifying width, depth, access time, control line configurations, and part type of any of a plurality of different synchronous memories. A nested loop process is used to develop, and apply to a synchronous memory being identified, trial control line configurations taken from ordered entries of tables representative of the plurality of synchronous memories. The width, depth, control line configurations, and part type are determined from the responses evoked from the synchronous memory being identified. The delay between a read command issued by the test system CPU and a reading of bit patterns from the synchronous memory is incremented in finite steps in successive write/read iterations until the bit pattern read is identified to the bit pattern written into the synchronous memory, thereby identifying the access time of the synchronous memory.Type: GrantFiled: July 16, 1997Date of Patent: January 30, 2001Assignee: Tanisys Technology, Inc.Inventors: Archer R. Lawrence, Jack C. Little
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Patent number: 6067648Abstract: A digital programmable delay which provides a series of pulses that are programmed in both pulse latency and trigger latency to control the operation of a memory module test system.Type: GrantFiled: March 2, 1998Date of Patent: May 23, 2000Assignee: Tanisys Technology, Inc.Inventors: Paul R. Hunter, Archer R. Lawrence, Jack C. Little
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Patent number: 6064948Abstract: A tester for use with a device under test includes a processor, a signal timing editor to create representations of signal waveforms and associated times, and a test program executable on the processor that schedules events based on information from the signal timing editor. The test program schedules different delays for the events to compensate for variations in time delays between different signals coupled to the device under test.Type: GrantFiled: March 2, 1998Date of Patent: May 16, 2000Assignee: Tanisys Technology, Inc.Inventors: Michael S. West, Archer R. Lawrence, Paul R. Hunter, Jack C. Little
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Patent number: 6008664Abstract: A system and method for reducing voltage stabilization time in a leakage current test system, and thereby reducing the time for measuring leakage currents in the I/O pins of an IC chip including CMOS DRAMs is disclosed. The method and system of the present invention accelerates leakage current testing time by precharging the capacitance of the I/O pins under test to a voltage near the settled voltage level, before measuring leakage current at the I/O pin contact points of packaged IC chips and assembled IC modules, and indicating when an I/O pin is defective.Type: GrantFiled: March 2, 1998Date of Patent: December 28, 1999Assignee: Tanisys Technology, Inc.Inventors: Allen Jett, Archer R. Lawrence
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Patent number: 5999468Abstract: A method and system for identifying the configuration of a memory module from a list of memory module parts uses contact test results on the memory module to determine data, control and address lines connected to the module. The memory module data, control and address line configurations as determined by the contact test are compared with data, control and address line configuration information from a list of potential memory parts. Non-matching memory parts from the list are eliminated from further testing, resulting in a reduced number of read and write cycles used by the tester to identify parts located on the memory module. The tester counts the number of data lines connected to the memory module to determine the width of the memory parts. The tester then performs a read and write operation to determine the number of memory banks located on the memory module and the control line configuration of the memory module.Type: GrantFiled: November 17, 1998Date of Patent: December 7, 1999Assignee: Tanisys Technology, Inc.Inventor: Allen B. Lawrence
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Patent number: 5995424Abstract: An automated, portable, and time conservative memory test system for identifying test parameters including type, control line configuration, depth, width, access time, and burst features of any one of a wide variety of synchronous memories including SDRAMs and SGRAMs, and whether an IC chip, bank, board or module, without requiring hardware modifications or additions to the memory device being identified, and without requiring storage of test patterns or characterizing, data in the memory device.Type: GrantFiled: July 16, 1997Date of Patent: November 30, 1999Assignee: Tanisys Technology, Inc.Inventors: Archer R Lawrence, Jack C Little
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Patent number: 5956280Abstract: A method and system for memory testers which detects the absence of contact between memory tester pins and memory module pins, and which identifies memory module pins which are shorted to a power supply terminal or to ground, pins which are shorted to other pins, and pins which are open.Type: GrantFiled: March 2, 1998Date of Patent: September 21, 1999Assignee: Tanisys Technology, Inc.Inventor: Allen B. Lawrence
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Patent number: 5933102Abstract: A touch sensor switch that responds to touching, or even to the proximity of an object, is disclosed. The switch includes a number of capacitance elements, or touch pads, that produce an effective capacitance dependent upon the physical proximity of the object. A microcontroller under control of a program stored in a read-only memory causes its I/O port to set a transient voltage on each capacitance element as a logic level. Each transient voltage is at variance with the capacitive element's preferred voltage level. The program then reads the I/O port, and hence the logic levels of the capacitance elements, as the capacitive elements revert to their preferred voltage levels, and calculates the proximity of the object, or touching, from relationships among recorded signals. The circuit may also be embodied in an application specific integrated circuit.Type: GrantFiled: September 24, 1997Date of Patent: August 3, 1999Assignee: Tanisys Technology, Inc.Inventors: Stephen J. Miller, Michael S. West
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Patent number: 5914902Abstract: An automated, portable, and time conservative memory test system for identifying test parameters including type, control line configuration, depth, width, access time, and burst features of any one of a wide variety of synchronous memories including SDRAMs and SGRAMs, and whether an IC chip, bank, board or module, without requiring hardware modifications or additions to the memory device being identified, and without requiring storage of test patterns or characterizing data in the memory device.Type: GrantFiled: July 14, 1998Date of Patent: June 22, 1999Assignee: Tanisys Technology, Inc.Inventors: Archer R Lawrence, Jack C Little
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Patent number: 5912852Abstract: An automated, portable, and time conservative memory test system for identifying test parameters including type, control line configuration, depth, width, access time, and burst features of any one of a wide variety of synchronous memories including SDRAMs and SGRAMs, and whether an IC chip, bank, board or module, without requiring hardware modifications or additions to the memory device being identified, and without requiring storage of test patterns or characterizing data in the memory device.Type: GrantFiled: July 14, 1998Date of Patent: June 15, 1999Assignee: Tanisys Technology, Inc.Inventors: Archer R. Lawrence, Jack C. Little
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Patent number: 5831597Abstract: A computer input device is used in conjunction with a mouse input device. The computer input device of the invention comprises a body having a resilient layer covered by a surface layer textured throughout the entirety of the surface for operation of the mouse. A printed circuit card is incorporated in the body between the resilient layer and the upper surface layer and includes a plurality of capacitive touch sensor pads. The card further includes electronic circuitry for operating the touch sensor pads to detect when a capacitive object, such as a fingertip, is in the proximity of a sensor pad. A touch need not apply force to register. The printed circuit card includes a guard ring pad surrounding the touch pads which detects the presence of the mouse over the sensor pads and indicates that any detected outputs from the sensor pads are not valid, but instead are due to the presence of the mouse.Type: GrantFiled: May 24, 1996Date of Patent: November 3, 1998Assignee: Tanisys Technology, Inc.Inventors: Michael S. West, Jennifer S. Nyland, Mitchell G. Burton
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Patent number: 5812472Abstract: A nested loop method for use in a memory test system to identify the width, depth, control line configuration, and part type of a synchronous memory, wherein bit patterns are retrieved from tables representative of a plurality of synchronous memories during execution of nested loops, from outer loop to inner loop, in the order of bank loop, RE loop, CE loop, CS loop, DQMB loop, and part type loop, and bits of an entry of a table occurring after a given entry are either a member of a superset or do not intersect bits of previous entries, and bits of an entry preceding the given entry are either a member of a subset or do not intersect bits of the given entry.Type: GrantFiled: July 16, 1997Date of Patent: September 22, 1998Assignee: Tanisys Technology, Inc.Inventors: Archer R. Lawrence, Jack C. Little
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Patent number: 5508700Abstract: A capacitance-sensitive switch unit including a capacitive element operable to produce an effective capacitance dependent upon the physical proximity of objects relative thereto, a first selector signal input connected to the capacitive element to enable a first input signal to charge the effective capacitance, a threshold signal producing circuit connected to the capacitive element, for producing a threshold signal which is rendered active when the effective capacitance charges to a pre-defined potential, a switching circuit for selectively connecting the capacitive element to the threshold signal producing circuit in response to a switching signal and a discharge control circuit connected to the capacitive element, for selectively discharging the effective capacitance independently of the input signal, in response to a discharge signal. Also disclosed is a switch array employing structure similar to the above.Type: GrantFiled: March 17, 1994Date of Patent: April 16, 1996Assignee: Tanisys Technology, Inc.Inventors: Thomas M. Taylor, Mitchell G. Burton