Patents Assigned to TECH Semiconductor Singapore Pte Ltd.
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Patent number: 7813893Abstract: A method that involves matching the trend of process outcome with the trend of process variables to identify the variables that have an impact on the process outcome is disclosed. The method for process trend matching comprises processing of raw data of process outcome and of process variables using an outlier filtering method, smoothing these data using common smoothing algorithm like Kernel, dividing smoothed raw data equally into time intervals, computing the gradients of the points at both ends of the time intervals, and translating the gradients into a scale based on the magnitude of the gradients. The following steps comprise comparing the process outcome and each process variable independently for same time frame, and assigning a score for both outcome and variable. The sum of the scores is then computed which is used to determine the quality of fit. A real-time monitoring system is then set up to monitor these variables for any drifts.Type: GrantFiled: January 18, 2007Date of Patent: October 12, 2010Assignee: TECH Semiconductor Singapore Pte LtdInventors: Kien Hoong Fong, Wei Fu, Jun Shi
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Patent number: 7750819Abstract: Methods and systems for detecting wafer shift/slide in a semiconductor process chamber have been disclosed. The vibration amplitude is measured in terms of acceleration because an increase in vibrational acceleration correlates with an increase of displacement of a wafer. The vibration of a chamber is measured. External vibratory forces acting on the chamber may be transmitted to the wafer inside the chamber. The methods/systems determine if there is a net resultant force that may cause an unconstrained wafer to move from its original position in a chamber by measuring the relative chamber vibrations in three orthogonal directions. A tri-axial or three uni-axial accelerometers are mounted on a preferably exterior wall of the chamber to measure its vibration amplitude. The signal obtained as a function of time is then compared against a predetermined alarm amplitude to provide notification for corrective action.Type: GrantFiled: April 7, 2008Date of Patent: July 6, 2010Assignee: TECH Semiconductor Singapore Pte LtdInventor: Khoon Peng Lim
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Patent number: 7680556Abstract: The present invention discloses a new data collection method employed by a middle layer between the host and the equipment, which improves the speed and consistency of data collection. The middle layer incorporated with the proposed data collection method functions as a data format converter as well as a data processor/classifier, which helps to filter and format messages before delivering data to the host or equipment. The proposed data collection method enables the middle layer to perform local reply, local data sampling, and group data polling, thus relieving processing resources of both the equipment and the host. This allows implementation of APC on older wafer fabrication processes using old equipment.Type: GrantFiled: November 15, 2004Date of Patent: March 16, 2010Assignee: TECH Semiconductor Singapore Pte. Ltd.Inventors: Boon Hong Sim, Ping Zhou
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Patent number: 7610111Abstract: Methods and systems for wafer lot ordering using including estimation of allowable queue time based on utilization loss and rework percentage have been achieved. The method invented comprises steps of ranking lots, allocating equipment to the exit step of queue time, calculating and determining the optimal allowable queue time based on utilization loss and rework percentage, calculating the next available time for equipment, calculating earliest release time, and releasing lot/batch and pre-assign it to the equipment at exit step. The present invention can be applied to other manufacturing lines than semiconductor manufacturing.Type: GrantFiled: February 13, 2007Date of Patent: October 27, 2009Assignee: TECH Semiconductor Singapore Pte LtdInventors: Cheng Lin, Nurulhuda Binte Jumahri
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Patent number: 7407871Abstract: A process for fabricating an MOS device specifically a DRAM device, featuring passivation of defects in regions of a semiconductor substrate wherein defects left unpassivated can deleteriously influence data retention time, has been developed. A high density plasma dry etching procedure used to define the DRAM conductive gate electrode can create unwanted defects in a region near the surface of uncovered portions of the semiconductor substrate during the high density plasma procedure over etch cycle. Implantation of a group V element such as arsenic can be used to passivate the unwanted plasma etch defects, thus reducing the risk of defect related device leakage phenomena.Type: GrantFiled: September 5, 2006Date of Patent: August 5, 2008Assignee: TECH Semiconductor Singapore Pte LtdInventors: Arvind Kumar, Keen Wah Chow, Devesh Kumar Datta, Subramanian Krishnan
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Patent number: 7363098Abstract: The present invention discloses a method that recognizes and uses the grouping patterns of process material by different machines at different process steps to identify potential problem machines causing the excursion in semiconductor manufacturing. The excursion could be a yield problem at the final test or at any inline electrical testing, metrology measurement, or inspection at different process steps. The potential problematic machines are listed in order of most likely to be problematic.Type: GrantFiled: December 19, 2005Date of Patent: April 22, 2008Assignee: TECH Semiconductor Singapore Pte LtdInventors: Choy Yow Ng, Ying Li Fan
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Patent number: 7248975Abstract: An apparatus and method for use is described which permits real time monitoring of build-up of particulate contamination in a wafer processing chamber. The apparatus is capable of monitoring particle build up in regions of a processing chamber which are not accessible by traditional optical particle scanners. An accelerometer is fastened to a body in the chamber upon which particulates deposit. The body is subjected to vibrations and produces a vibration signal which is detected by the accelerometer. The signal is processed to form a frequency spectrum of vibration amplitudes. Frequencies in a selected band are directly proportional to the particulate build up on the body. The invention is applied to a wafer annealing tool with a rotatable platform wherein particles deposit on a support body under the wafer. The method and apparatus have been shown to be reliable and accurate as well as cost effective and easily implemented.Type: GrantFiled: September 20, 2005Date of Patent: July 24, 2007Assignee: TECH Semiconductor Singapore Pte LtdInventors: Khoon Peng Lim, Lai Seng Foo
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Patent number: 7163435Abstract: CMP pad conditioning processes have been monitored and controlled by detecting the vibrational spectrum of a sensor mounted on the conditioner support arm. An accelerometer is used as the detector so that vibrational velocity (which correlates with pad wear) can be measured, rather than displacement or acceleration. After the vibrational spectrum has been transformed to its frequency domain equivalent, it is monitored for the presence of abnormal peaks in order to control the conditioning process.Type: GrantFiled: January 31, 2005Date of Patent: January 16, 2007Assignee: Tech Semiconductor Singapore Pte. Ltd.Inventors: Khoon Peng Lim, Kok Eng Lee
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Patent number: 7121927Abstract: An improved design for a retaining ring for a chemical mechanical poling machine is described which provides superior flexibility and instantaneous in-situ control of the polishing rate in the edge region of a wafer. The design has a plurality of straight slurry delivery groves, angled in the direction of rotation of said ring wherein each alternate channel is recessed away from the inner circumference of the bottom, pad contacting, surface, of said retaining ring by a recess which extends upward from the bottom surface only sufficiently to prevent contact of the retaining ring with the polishing pad in the area of the recess. Each recess curves outwardly towards the inner circumference of the retaining ring in a manner to form a symmetrical segmented tab with a rounded edge, tangent to the inner circumference of the retaining ring, and meeting the inner circumference at the exit end of an adjacent non-recessed slurry channel. For a 200 mm.Type: GrantFiled: March 6, 2006Date of Patent: October 17, 2006Assignee: Tech Semiconductor Singapore Pte. Ltd.Inventors: Yew Hoong Phang, Jianguang Chang
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Patent number: 7029933Abstract: Both the sensitivity and the reproducibility of processes for measuring low density ion implant doses near a semiconductor surface have been improved by first forming a thermal oxide layer on the surface and then adjusting the implant profile so that it peaks at the semiconductor-oxide interface. Additionally, variations in the initial wafer surface condition have been minimized by controlling the charging dose and sequence prior to performing the measurements.Type: GrantFiled: June 22, 2004Date of Patent: April 18, 2006Assignee: Tech Semiconductor Singapore Pte. Ltd.Inventors: Siew Fong Wee, Luey Chwan Liong
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Patent number: 6893983Abstract: A thermal activated SACVD method for depositing a phosphorus oxide layer onto a silicon oxide wafer comprising the steps of: loading an SACVD device with a silicon oxide wafer; depositing a phosphorus doped oxide (PSG) layer on the USG layer using pure oxygen and a phosphorus and silicon source; purging the SACVD device; and depositing a boron and phosphorus doped oxide (BPSG) layer on the PSG layer.Type: GrantFiled: September 13, 2001Date of Patent: May 17, 2005Assignee: TECH Semiconductor Singapore Pte Ltd.Inventors: Jian Sun, Hing Ho Au, Yew Hoong Phang