Abstract: Systems and methods for controlling transmission of signals are described. A camera-side modem is configured to receive two signals from a video camera and to extract a received passband signal from a transmission line. A detector in the camera-side modem generates an alarm signal when disruption or loss of the received passband signal is identified. An enable signal is used to control transmission of at least one of the baseband video signal and the passband video signal. The passband signal may be identified by an estimate of mean square error in a quadrature amplitude demodulator, a measurement of reliability provided by a constellation detector, a measurement of reliability based on a sequence of frame synchronizations and/or an estimate of mean square error in an equalizer. The detector may monitor a gain factor in an automatic gain control module of the camera-side modern and/or a magnitude of the received passband signal.

Abstract: Systems and methods for controlling transmission of signals are described. A camera-side modem is configured to receive two signals from a video camera and to extract a received passband signal from a transmission line. A detector in the camera-side modem generates an enable signal when the received passband signal is identified. The enable signal is used to control transmission of at least one of the baseband video signal and the passband video signal. The passband signal may be identified by an estimate of mean square error in a quadrature amplitude demodulator, a measurement of reliability provided by a constellation detector, a measurement of reliability based on a sequence of frame synchronizations and/or an estimate of mean square error in an equalizer. The detector may monitor a gain factor in an automatic gain control module of the camera-side modem and/or a magnitude of the received passband signal.

Abstract: The present invention provides a novel symbol timing recovery method for VSB receivers. Systems are described that comprise a timing error detector (TED) that produces an exact symbol timing error even in the presence residual carrier phase offset, loop filter that controls the characteristics of acquisition and tracking of digital PLL loop, Voltage/Numerically Controlled Oscillator (VCO/NCO) that adjusts the sampling instant and phase, A/D converter that samples a continuous VSB input signal, and a interpolating squared root raised cosine filter that performs both matched filtering and a compensation of constant timing offset of quarter symbol caused by the invented TED. The timing error detector in this invention comprises an envelope detector, band pass filter, squaring block, high pass filter, and decimator.

Abstract: Systems and methods are described that may be used to detect and correct carrier phase offset in a signal. A phase offset corrector receives an equalized signal representative of a quadrature amplitude modulated signal and derives a phase-corrected signal from the equalized signal. The equalized signal is sliced to obtain real and imaginary sequences and a frame synchronizer performs a correlation of the real and imaginary sequences with corresponding parts of a stored frame-sync pseudo-random sequence. Phase correction is based on the maximum real and imaginary values of the correlation. The signal is typically quadrature amplitude modulated signal is modulated using punctured trellis codes. Quadrature phase shift keying modulation, 16-QAM, 64-QAM and other QAM schemes may be used.

Abstract: An equalizer and methods for equalizing a cable-borne signal are described. The cable-borne signal includes a digital signal and a baseband analog signal separated by frequency. Distortions are removed from the digital signal and an analog equalizer compensates for attenuations of the analog signal caused by the cable based on equalization settings of a digital equalizer. A baseband analog filter can be selected based on an estimate calculated by the digital equalizer of difference in attenuation at different frequencies.

Abstract: The present invention provides a novel technique for improving the performance of equalizers by reducing the effects of error propagation in equalizers that use a Viterbi Decoder. Methods and systems are described that can improve the performance of equalizers by reducing the effects of error propagation in equalizers that use a Viterbi Decoder. Systems and methods of symbol correction in prediction decision feedback equalization (“pDFE”) architectures are described. Systems are described that include one or more enhanced Viterbi decoders together with novel methods of symbol correction to obtain better system performance. Systems and methods are described that utilize dual pDFEs and can use a blending algorithm to reduce errors in symbol decoding. Dual pDFEs are described that include forward and backward Viterbi decoders wherein the backward Viterbi decoded may operate on time reversed data blocks and with some degree of latency.

Abstract: Novel systems and methods are described in which performance of equalizers can be improved by reducing the effects of error propagation in equalizers that use a Viterbi Decoder. Systems and methods of symbol correction in prediction decision feedback equalization architectures are described including systems and methods that include an enhanced Viterbi decoder and novel methods of symbol correction to obtain better system performance. The use of a blending algorithm is described to reduce errors in symbol decoding. Histories of deep trace back depth symbols can be maintained to enable more accurate decisions. Systems and methods described can provide advantage in the feedback path of adaptive equalizers in trellis decoders. The invention provides novel techniques for improving the performance of equalizers by reducing the effects of error propagation in equalizers that use a Viterbi Decoder.

Abstract: Systems and methods for operating cameras are described. An image signal received from an image sensor can be processed as a plurality of video signals representative of the image signal. An encoder may combine baseband and digital video signals in an output signal for transmission over a cable. The video signals may include substantially isochronous baseband and digital video signals. The baseband video signal can comprise a standard definition analog video signal and the digital video signal may be modulated before combining with the baseband video signal and/or transmitting wirelessly. The digital video signal may be a compressed high definition digital video signal. A decoder demodulates an upstream signal to obtain a control signal for controlling the position and orientation of the camera and content of the baseband and digital video signals.

Abstract: Novel systems and methods are described in which performance of equalizers can be improved by reducing the effects of error propagation in equalizers that use a Viterbi Decoder. Systems and methods of symbol correction in prediction decision feedback equalization architectures are described including systems and methods that include an enhanced Viterbi decoder and novel methods of symbol correction to obtain better system performance. The use of a blending algorithm is described to reduce errors in symbol decoding. Histories of deep trace back depth symbols can be maintained to enable more accurate decisions. Systems and methods described can provide advantage in the feedback path of adaptive equalizers in trellis decoders. The invention provides novel techniques for improving the performance of equalizers by reducing the effects of error propagation in equalizers that use a Viterbi Decoder.

Abstract: The present invention provides a novel technique for improving the performance of equalizers by reducing the effects of error propagation in equalizers that use a Viterbi Decoder. Methods and systems are described that can improve the performance of equalizers by reducing the effects of error propagation in equalizers that use a Viterbi Decoder. Systems and methods of symbol correction in prediction decision feedback equalization (“pDFE”) architectures are described. Systems are described that include one or more enhanced Viterbi decoders together with novel methods of symbol correction to obtain better system performance. Systems and methods are described that utilize dual pDFEs and can use a blending algorithm to reduce errors in symbol decoding. Dual pDFEs are described that include forward and backward Viterbi decoders wherein the backward Viterbi decoded may operate on time reversed data blocks and with some degree of latency.

Abstract: A method and system for channel tracking in an adaptive equalizer for a digital data receiver. The method includes determining a first set of tap weights and a second set of tap weights of the equalizer, and determining a difference between the first and second sets of tap weights. The method also includes determining an error estimate based on symbols received at the receiver, comparing the error estimate with a divergence threshold, and determining a step size factor based on the difference and the comparison.

Abstract: The present invention provides a novel symbol timing recovery method for VSB receivers. Systems are described that comprise a timing error detector (TED) that produces an exact symbol timing error even in the presence residual carrier phase offset, loop filter that controls the characteristics of acquisition and tracking of digital PLL loop, Voltage/Numerically Controlled Oscillator (VCO/NCO) that adjusts the sampling instant and phase, A/D converter that samples a continuous VSB input signal, and a interpolating squared root raised cosine filter that performs both matched filtering and a compensation of constant timing offset of quarter symbol caused by the invented TED. The timing error detector in this invention comprises an envelope detector, band pass filter, squaring block, high pass filter, and decimator.

Abstract: The present invention provides a novel symbol timing recovery method for VSB receivers. Systems are described that comprise a timing error detector (TED) that produces an exact symbol timing error even in the presence residual carrier phase offset, loop filter that controls the characteristics of acquisition and tracking of digital PLL loop, Voltage/Numerically Controlled Oscillator (VCO/NCO) that adjusts the sampling instant and phase, A/D converter that samples a continuous VSB input signal, and a interpolating squared root raised cosine filter that performs both matched filtering and a compensation of constant timing offset of quarter symbol caused by the invented TED. The timing error detector in this invention comprises an envelope detector, band pass filter, squaring block, high pass filter, and decimator.

Abstract: The present invention provides a novel symbol timing recovery method for VSB receivers. Systems are described that comprise a timing error detector (TED) that produces an exact symbol timing error even in the presence residual carrier phase offset, loop filter that controls the characteristics of acquisition and tracking of digital PLL loop, Voltage/Numerically Controlled Oscillator (VCO/NCO) that adjusts the sampling instant and phase, A/D converter that samples a continuous VSB input signal, and a interpolating squared root raised cosine filter that performs both matched filtering and a compensation of constant timing offset of quarter symbol caused by the invented TED. The timing error detector in this invention comprises an envelope detector, band pass filter, squaring block, high pass filter, and decimator.

Abstract: A video decoder for decoding a composite video signal. The decoder includes an analog-to-digital converter (ADC), an input resampler, and a Y/C separator, all coupled in series. The ADC receives and digitizes the composite video signal to generate ADC samples. The input resampler receives and resamples the ADC samples with a first resampling signal to generate resampled video samples. The Y/C separator receives and separates the resampled video samples into luminance and chrominance components. The Y/C separator includes a delay element configured to receive the resampled video samples and provide a variable amount of delay. The variable amount of delay can be adjustable from line to line, and is typically based on an approximated duration of a video line.

Abstract: A sample rate converter that includes a number of selector elements coupled to a summing circuit. Each selector element receives a respective set of one or more processed data samples and provides one of the processed data samples. Each processed data sample is generated by delaying an input sample by zero or more clock cycles and scaling the sample by a particular scaling factor (e.g. 2N, where N is 0, 1, 2, and so on). The summing circuit receives and combines the processed data samples from the selector elements to generate an output sample. A delay and scaler circuit can receive the input sample and provide one set of processed data samples for each selector element. The delay and scaler circuit can include one or more delay elements coupled in series and to a scaling circuitry that scales selected ones of the input and delayed samples. The scaling can be implemented by simply bit-shifting the samples. The elements of the sample rate converter can be configured to implement a K-tap, P-phase interpolator.

Abstract: Techniques for enhancing edges in video signals while reducing the amounts of undershoots and overshoots. A video signal is processed to generate a first signal indicative of detected edges in the video signal. The first signal can be generated by lowpass filtering the video signal to generate a lowpass signal and subtracting the lowpass signal from a luminance signal that has been extracted from the video signal. The first signal is then processed with a “non-linear” transfer function to generate a second signal having enhanced edges. The second signal is used as the correction or enhancement signal, and is added to the lowpass signal to provide an output signal having enhanced edges with reduced or minimal amounts of undershoots and overshoots.