Abstract: A circuit for recovering the data encoded in several VBI channels without requiring a large number of gates. An analog to digital converter (ADC) and a clock and data recovery circuit may be associated with one of several possible channels. ADC over samples each VBI channel, and clock and data recovery circuit determines which subset of the over samples represent the encoded data by examining the over sampled samples. The selected subset may be stored in a shared memory and a equalizer may process the subset of samples of all channels to perform tasks such as deghosting. Due to the shared equalizer, the number of required gates may be minimized.

Abstract: Data stored internally in a television system is modified conveniently. New data is stored on a video tape. A user of a television system simply needs to play the video tape on a video cassette player to change pre-stored data in the television system. The video signal resulting from playing the video tape is provided to the television system. The television system examines the received video signal to recover the encoded new data and uses the new data to modify the pre-stored data. For example, the pre-stored data may be replaced by the new data.

Abstract: A low pass digital filter using cascade polyphase recursive digital signal processing circuit. The filter in the receive direction may contain a re-sampling Hogenauer filter followed by an equalizer filter to correct for its non-flat pass-band spectral response. The output of the spectral equalizer may be processed by a poly-phase re-sampling filter to reduce the sample rate. A clean-up filter may insert two stop-band spectral intervals in the frequency response of the earlier stages. The filter in the receive direction may be implemented by using similar components in the reverse order.

Abstract: A television system (TV) which enables a user to view display represented by a television signal as well as to access data network applications. The TV includes an on-screen-display (OSD) controller which stores the network application data and other display entities in a memory module as separate bit maps. A single image for display on a TV display screen is generated by overlaying all the display entities (including television signal, network application data, pointer, and low resolution data) according to a predetermined priority. Display entities (other than TV signal) are stored in separate portions of the memory module as independent surfaces to enable the displays of individual display entities to be generated and modified according to the individual display entity requirements.

Abstract: A clock generation circuit for use in a television system displaying images encoded in television signals and images represented by network application data. The clock generation circuit generates a clock signal synchronized with HSYNC signals of the television signals. The clock generation circuit includes a phase-lock-loop (PLL) circuit and a tracking block. PLL circuit includes an oscillator (e.g., VCO) driven by an error signal to generate an internal periodic signal having frequency substantially equal to the frequency of the desired clock signal. The tracking block includes a resettable VCO (RVCO) driven by the error signal. A restart signal is asserted prior to the expected arrival time of the HSYNC edge to cause the RVCO to stop generating the desired clock signal. The restart signal is deasserted on receiving the HSYNC edge to cause the RVCO to start generating the clock signal. Accordingly, the clock signal is synchronized with the HSYNC signal.

Abstract: A method of recovering synchronization signals contained in a composite video signal. The synchronization signals are generally represented by voltage levels less than the blanking level of the video signal, and display data is represented by blanking level. A digital circuit controls a biasing circuit to generate a biasing voltage. A video signal is biased using the biasing voltage and the resulting biased video signal is provided as an input to an operational amplifier. A second input of the operational amplifier is driven by a reference voltage. The digital circuit monitors the output of the operational amplifier and controls the biasing voltage to cause the operational amplifier to clip the display data from the biased video signal and generate a signal representing synchronization signals.

Abstract: A memory controller for controlling accesses to a memory storing display entities including network application data displayed on a display screen of a television system. For performing a display screen refresh operation, the network application data is retrieved with a predetermined period. Accordingly, the memory controller determines an expected time for receiving the next request for retrieving the network application data for screen refresh. The memory controller blocks any lower priority memory access requests from a few clock cycles prior to the determined expected time. As a result, the requests for retrieving network application data can be serviced in an acceptable time.

Abstract: A television system for displaying images having adjacent horizontal blocks with sharp contrast. In general, such sharp contrasts can cause the drive voltage (Hv) applied to an anode of a CRT display unit to change. The changes typically result in distortions in the displayed images. A correction logic is employed to regulate the voltage source that supplies the voltage to the anode of the CRT display unit. The correction logic examines the digital data representation of the images to determine the extent of contrast, and supplies a corresponding correction voltage to regulate the voltage source. Due to the correction voltage, a constant drive voltage is supplied to the anode. The distortions are thus minimized or eliminated.

Abstract: A television system (TV) with an interlaced display screen for displaying network application data. A flicker filter is preferably implemented as an infinite impulse response (IIR) filter to eliminate sharp transitions in the network application data images. A random access memory is used to store the lines of the filtered images and any adjacent lines used for the filtering operation. Alternate lines of the filtered images are retrieved from the random access memory to provide an interlaced image of the filtered network application data images. The interlaced images are displayed on an interlaced display unit of a television system.

Abstract: A television system (TV) which enables a user to view display represented by a television signal as well as to access data network applications. The TV includes an on-screen-display (OSD) controller which stores the network application data and other display entities in a memory module as separate bit maps. A single image for display on a TV display screen is generated by overlaying all the display entities (including television signal, network application data, pointer, and low resolution data) according to a predetermined priority. Display entities (other than TV signal) are stored in separate portions of the memory module as independent surfaces to enable the displays of individual display entities to be generated and modified according to the individual display entity requirements.

Abstract: A television system for recovering the digital data encoded in a television signal at an encoding frequency. The television signal is sampled at a frequency much higher than the encoding frequency, and the resulting sampled data elements are stored in a memory. Sampled data elements corresponding to a clock run-in portion (synchronization signal portion) of the television signal are examined to a samples interval equal to the number of samples per encoding clock periods. Transitions in the values of data elements are determined by examining consecutive sampled data elements. In general, sampled data elements are selected with an interval equal to the determined samples interval as representing the encoded digital data elements. However, the selection sequence is adjusted according to the transitions to ensure that the samples in only the stable portions of the television signal are selected.

Abstract: A television system (TV) with an interlaced display screen for displaying network application data. Pixel data elements representing network application data display are received in a non-interlaced mode. The received data is filtered to reduce sharp transitions in the display. The filtered data is provided in an interlaced format (i.e., only alternate lines of a frame) for display on the television display screen. The interlaced image display is combined with the television signal display by selecting one of them on point by point basis. Flicker is reduced substantially in the final display of network application data due to the filtering.

Abstract: A memory controller for controlling accesses to a memory storing display entities including network application data displayed on a display screen of a television system. For performing a display screen refresh operation, the network application data is retrieved with a predetermined period. Accordingly, the memory controller determines an expected time for receiving the next request for retrieving the network application data for screen refresh. The memory controller bolcks any lower priority memory access requests from a few clock cycles prior to the determined expected time. As a result, the requests for retrieving network application data can be serviced in an acceptable time.

Abstract: A television system (TV) with an interlaced display screen for displaying network application data. Pixel data elements representing network application data display are received in a non-interlaced mode. The received data is filtered to reduce sharp transitions in the display. The filtered data is provided in an interlaced format (i.e., only alternate lines of a frame) for display on the television display screen. The interlaced image display is combined with the television signal display by selecting one of them on point by point basis. Flicker is reduced substantially in the final display of network application data due to the filtering.

Abstract: A television system (TV) which enables a user to view display represented by a television signal as well as to access data network applications. The TV includes an on-screen-display (OSD) controller which stores the network application data and other display entities in a memory module as separate bit maps. A single image for display on a TV display screen is generated by overlaying all the display entities (including television signal, network application data, pointer, and low resolution data) according to a predetermined priority. Display entities (other than TV signal) are stored in separate portions of the memory module as independent surfaces to enable the displays of individual display entities to be generated and modified according to the individual display entity requirements.