Abstract: A method and system for analyzing and measuring image quality between two images. A series of conversions and transformations of image information are preformed to produce a single measure of quality. A YCrCb frame sequence is first converted using RGB conversion to an RGB frame sequence. The resulting RGB frame sequence is converted using spherical coordinate transform (SCT) conversion to SCT images. A Gabor filter is applied to the SCT images to produce a Gabor Feature Set, and a statistics calculation is applied to the Gabor Feature Set. The resulting Gabor Feature Set statistics are produced for both the reference frame and the frame to be compared. Quality is computed for these Gabor Feature Set statistics to produce a video quality measure. Spectral decomposition of the frames is also performable for the Gabor Feature Set, rather than the statistics calculation, allowing graphical comparison of results for the compared frames.

Abstract: A progressive video frame is detected in a sequence of video fields, wherein the sequence of video fields includes a target video field. Detection includes generating one or more metrics by comparing the target video field with an immediately preceding and/or immediately succeeding video field. The metrics are compared with one or more threshold values. The immediately preceding and/or immediately succeeding video field is determined to have been derived from a same progressive video frame as the target video field if the one or more metrics are less than their respective threshold values. The metrics in this case may be indicative of a quantity of interlace artifacts. Alternatively, metrics indicative of an amount of represented motion may be derived by comparing a target video field with each of an immediately preceding and immediately succeeding video field.

Abstract: Video images are processed to detect image motion among sequential images (e.g., progressive non-interlaced images of a video signal and/or interlaced fields of a video signal), each image being represented using a plurality of pixels. Exemplary embodiments replace block-based motion estimation with pixel-based motion estimation. A correlation surface is generated for every pixel in a reference image, from which a motion vector and confidence metric (i.e., a measure of confidence in the accuracy of the motion vector) are extracted for each pixel.

Abstract: Selectively distributing a plurality of data items to a plurality of hardware destinations that share a common bus involves, for each one of the data items, determining which of the hardware destinations the data item should be distributed to, wherein at least one of the data items should be distributed to two or more hardware destinations. The data item is then supplied to the common bus and, for each of the hardware destinations to which the data item should be distributed, a corresponding hardware destination signal is generated that causes the data item to be received in the hardware destination from the common bus, wherein for each data item, the corresponding hardware destination signals are generated substantially simultaneously. This may be applied in a number of scenarios, including the distribution of data items to a plurality of processor boards, and to the distribution of data items to a plurality of channels within a single processor board.

Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. In one aspect, each of the processing elements includes one or more addressable storage means and other elements arranged in a pipelined architecture. The controller includes means for receiving a high level instruction, and converting each instruction into a sequence of one or more processing element microinstructions for simultaneously controlling each stage of the processing element pipeline. In doing so, the controller detects and resolves a number of resource conflicts, and automatically generates instructions for registering image operands that are skewed with respect to one another in the processing element array.

Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. In one aspect, each of the processing elements includes one or more addressable storage means and other elements arranged in a pipelined architecture. The controller includes means for receiving a high level instruction, and converting each instruction into a sequence of one or more processing element microinstructions for simultaneously controlling each stage of the processing element pipeline. In doing so, the controller detects and resolves a number of resource conflicts, and automatically generates instructions for registering image operands that are skewed with respect to one another in the processing element array.

Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a pattern register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming “supercells” within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register.

Abstract: An apparatus for processing data has a plurality of single-bit processing elements coupled together to form an m×n processing element array, where m is an integer number of rows and n is an integer number of columns. Each processing element has addressable storage for storing pixel data in an array format in which each addressable storage holds all of the bits associated with one pixel; and the processing element array includes a mechanism for providing direct read/write access to the addressable storage located in any addressed row of the processing element array without requiring that data be passed through other rows of the array.

Abstract: Bit-serial processors quickly multiply multiple-bit operands using significantly fewer clock cycles as compared to conventional bit-serial implementations. Exemplary embodiments process groups of operand bits simultaneously to provide the significant speed increases. Advantageously, however, the exemplary embodiments utilize logic and memory architectures which are fully compatible with, and fully useful for, conventional bit-serial applications, and the embodiments thus provide fast multiple-bit multiplications while at the same time providing all of the advantages typically associated with conventional bit-serial processors.

Abstract: Methods and apparatus for quickly dividing multiple-bit operands using bit-serial processors include strategies for eliminating the number of steps required to execute conventional division operations. According to an exemplary embodiment, a conditional subtraction step, based on a quotient bit computed during a given pass, is combined with a compare step which is used to compute a next quotient bit and which, according to conventional techniques, is ordinarily computed during a subsequent pass. Additionally, exemplary embodiments provide a zero/non-zero mask for denominator bits which extend beyond a current most significant remainder bit during a given pass. As a result, not all denominator bits need be considered during every pass. Advantageously, the methods and apparatus of the invention can provide approximately a 3 to 1 speed improvement as compared to conventional techniques.

Abstract: A memory-like I/O system is provided for interfacing a processing element array with a host system. The I/O system includes cornerturn logic for converting data written to the processing element array from horizontal format to vertical format and for converting data read from the processing element array from vertical format to horizontal format. Addressable interface memory is provided and includes a first bank for receiving and storing data which has been output from the cornerturn logic and for outputting that data for delivery to the processing element array. The addressable interface memory includes a second bank for receiving and storing data which has been output from the processing element array and for outputting that data for delivery to the cornerturn logic. The interface of the invention can provide support for concurrent I/O and processing, thereby allowing processing and I/O operations to proceed in parallel.

Abstract: A parallel processor has a controller for generating control signals, and a plurality of identical processing cells, each of which is connected to at least one neighboring cell and responsive to the controller for processing data in accordance with the control signals. Each processing cell includes a memory, a first register, a second register, and an arithmetic logic unit (ALU). An input of the first register is coupled to a memory output. The output of the first register is coupled to a second register located in a neighboring cell. An input of the second register is coupled to receive an output from a first register located in a neighboring cell. The output of the second register is coupled to an input of the ALU. In another feature, mask logic is interposed between A and B operand sources, and two inputs of the ALU.

Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a mask register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming "supercells" within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register.