Abstract: Disclosed are various exemplary embodiments of a clock recovery apparatus for recovering clock signals of multiple data channels. In one exemplary embodiment a clock recovery apparatus for a plurality of data channels may include a plurality of channel blocks, where each channel block may include a frequency detection block configured to generate an intermediate signal based on a respective data signal received from a respective data channel and a global signal, and a recovery block configured to recover a clock signal for the respective data channel in response to the respective data signal and the global signal. The apparatus may also include a global signal generation block configured to receive and combine the intermediate signals from the plurality of channel blocks to generate the global signal.

Abstract: The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)-based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jitter-tolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for low-power applications since a phase shifter in the data path, which is one of the most power-hungry blocks in conventional DPLL designs, is not required.

Abstract: Exemplary embodiments of the present invention relate to an internal jitter tolerance tester. The internal jitter tolerance tester may include a digital loop filter consisting of a cyclic accumulator which accumulates a phase detector's output, a gain multiplier, an internal accumulated jitter generator (or an internal sinusoid jitter generator), and a phase rotator (or DCO) controller. The internal accumulated jitter generator may include a PRBS generator, a digital loop filter, an accumulator, and a gain controller. The accumulated jitter generator also may be replaced with the internal sinusoid jitter generator. The internal sinusoid jitter generator may include a counter, a sinusoid jitter profile lookup table, and a gain controller.

Abstract: A variable-precision distributed arithmetic (VPDA) multi-input multi-output (MIMO) equalizer is presented to reduce the size and dynamic power of 112 Gbps dual-polarization quadrature phase-shift-keying (DP-QPSK) coherent optical communication receivers. The VPDA MIMO equalizer compensates for channel dispersion as well as various non-idealities of a time-interleaved successive approximation register (SAR) based analog-to-digital converter (ADC) simultaneously by using a least mean square (LMS) algorithm. As a result, area-hungry analog domain calibration circuits are not required. In addition, the VPDA MIMO equalizer achieves 45% dynamic power reduction over conventional finite impulse response (FIR) equalizers by utilizing the minimum required resolution for the equalization of each dispersed symbol.

Abstract: Exemplary embodiments of the present invention relate to an internal jitter tolerance tester. The internal jitter tolerance tester may include a digital loop filter consisting of a cyclic accumulator which accumulates a phase detector's output, a gain multiplier, an internal accumulated jitter generator (or an internal sinusoid jitter generator), and a phase rotator (or DCO) controller. The internal accumulated jitter generator may include a PRBS generator, a digital loop filter, an accumulator, and a gain controller. The accumulated jitter generator also may be replaced with the internal sinusoid jitter generator. The internal sinusoid jitter generator may include a counter, a sinusoid jitter profile lookup table, and a gain controller.

Abstract: Exemplary embodiments of the present invention relate to a clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor. The Kalman gain extractor includes an off chip digital processor which receives a phase update information from the CDR outputs an estimated optimum Kalman gain obtained by extracting the standard deviation of step sizes of the accumulation jitter from the power spectral density (PSD) of the phase update information, and a on chip digital loop filter consists of a cyclic accumulator which accumulates the phase detector's output, a gain multiplier and a phase interpolator (or DCO) controller. The off chip digital processor includes a storage register, a fast Fourier transform (FFT) processor and an optimum Kalman gain estimator. The storage register stores the phase update information, from which the FFT processor extracts the PSD of the absolute input jitter.

Abstract: Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed.

Abstract: Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.

Abstract: Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response.

Abstract: Disclosed is a statistical reference oscillator that includes: a stochastic reference clock generator which receives an input data outputs a reference signal obtained by dividing the received input data at a first frequency division ratio; a frequency divider which divides the frequency of an output signal at a second frequency division ratio and outputs a feedback signal; a frequency detector which outputs a difference signal based on a difference between the reference signal and the feedback signal; and an output signal generator which outputs the output signal based on the difference signal.

Abstract: Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response.

Abstract: Disclosed are various exemplary embodiments of a clock recovery apparatus for recovering clock signals of multiple data channels. In one exemplary embodiment a clock recovery apparatus for a plurality of data channels may include a plurality of channel blocks, where each channel block may include a frequency detection block configured to generate an intermediate signal based on a respective data signal received from a respective data channel and a global signal, and a recovery block configured to recover a clock signal for the respective data channel in response to the respective data signal and the global signal. The apparatus may also include a global signal generation block configured to receive and combine the intermediate signals from the plurality of channel blocks to generate the global signal.

Abstract: Exemplary embodiments of the present invention relate to a clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor. The Kalman gain extractor includes an off chip digital processor which receives a phase update information from the CDR outputs an estimated optimum Kalman gain obtained by extracting the standard deviation of step sizes of the accumulation jitter from the power spectral density (PSD) of the phase update information, and a on chip digital loop filter consists of a cyclic accumulator which accumulates the phase detector's output, a gain multiplier and a phase interpolator (or DCO) controller. The off chip digital processor includes a storage register, a fast Fourier transform (FFT) processor and an optimum Kalman gain estimator. The storage register stores the phase update information, from which the FFT processor extracts the PSD of the absolute input jitter.