Patents Assigned to TEREPAC Corporation
  • Patent number: 8759713
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process bonds multiple interconnect wires to bond pads with electrical linkages between the bond pads and then subsequently separates the adjacent bond pads.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: June 24, 2014
    Assignee: Terepac Corporation
    Inventor: Jayna Sheats
  • Publication number: 20130192523
    Abstract: The present invention discloses systems and methods for printing functional blocks from a plurality of printheads to a target substrate. In exemplary embodiments, the printing system comprises a main printhead for the majority of printing process, and a secondary printhead for supplemental printing. The system further comprises a controller, utilizing a positioning intelligence system to distribute the printing of the functional blocks between the main printhead and the secondary printhead, to minimize the motions of the printheads while maximize the printing speed.
    Type: Application
    Filed: March 4, 2013
    Publication date: August 1, 2013
    Applicant: TEREPAC CORPORATION
    Inventor: TEREPAC CORPORATION
  • Publication number: 20130193561
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.
    Type: Application
    Filed: March 5, 2013
    Publication date: August 1, 2013
    Applicant: TEREPAC CORPORATION
    Inventor: TEREPAC CORPORATION
  • Patent number: 8153517
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process coats the component surfaces to facilitate the bonding of the bond pads. In another aspect, the present process coats the bond pads with shelled capsules to facilitate the bonding of the bond pads.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: April 10, 2012
    Assignee: Terepac Corporation
    Inventor: Jayna Sheats
  • Patent number: 8124452
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The process can separate the integrated circuits into an analog portion and a digital portion with the analog portion comprising passive components utilizing dielectric materials different than silicon dioxide and active components utilizing channel materials different than substrate single crystal silicon.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: February 28, 2012
    Assignee: TEREPAC Corporation
    Inventor: Jayna Sheats