Patents Assigned to Ternarylogic LLC
  • Publication number: 20100164548
    Abstract: An n-valued switch with n?2 and n>2 and n>7, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances of a physical phenomenon, an instance representing a state. N-valued inverters are also disclosed. Different types of signals are disclosed, including optical signals with different wavelengths, electrical signals with different frequencies and signals represented by a presence of a material. A kit including an n-valued switch is also disclosed.
    Type: Application
    Filed: February 23, 2010
    Publication date: July 1, 2010
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7725779
    Abstract: Method and apparatus for writing scrambled multi-value data to a physical media and for reading scrambled multi-value data from a physical media, are disclosed. The physical media can be an optical disk. The scrambling can be performed by a multi-valued LFSR scrambler and the descrambling can be performed by a multi-valued LFSR descrambler. Further, the multi-valued data that is scrambled can include synchronization data and/or user data. Error correction coding can be used during the writing process and processing to correct for errors can be used during the reading process. Also, methods and apparatus for synchronizing multi-valued data written to and read from physical media are disclosed. Multi-value correlation methods and apparatus are also disclosed.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: May 25, 2010
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7696785
    Abstract: An n-valued switch with n?2, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances of a physical phenomenon, an instance representing a state. N-valued inverters are also disclosed. Different types of signals are disclosed, including optical signals with different wavelengths, electrical signals with different frequencies and signals represented by a presence of a material. A kit including an n-valued switch is also disclosed.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: April 13, 2010
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7659839
    Abstract: A method for coding a message of a plurality of m-state symbols into a coded message of n-state symbols wherein n>m is disclosed. A method to make the distribution of states of n-state symbols a uniform distribution is also disclosed. A coding rule is initiated based on a distribution of states of m-state symbols. A method of coding the coding rule by transposition is also provided. In one embodiment a coded message of n-state symbols has symbols that each have a unique state. A system for executing the coding and decoding methods is also disclosed.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: February 9, 2010
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7656196
    Abstract: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: February 2, 2010
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7643632
    Abstract: Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: January 5, 2010
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20090234900
    Abstract: Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and apparatus to efficiently perform the function a0b1+a1b0 on multi-value signals are disclosed. Also an efficient method of processing large binary signals is disclosed.
    Type: Application
    Filed: May 27, 2009
    Publication date: September 17, 2009
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7580472
    Abstract: Method and apparatus for generating ternary and multi-valued Gold sequences, are disclosed. Also methods to detect ternary and multi-valued sequences are disclosed. The detection can be performed by a ternary or multi-valued LFSR descrambler when the sequences are generated by an LFSR based sequence generator. A wireless system which can assign additional sequences to designated users is also disclosed. The wireless system can also transfer information to user equipment that enables methods for sequence generation and sequence detection.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: August 25, 2009
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7562106
    Abstract: Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and apparatus to efficiently perform the function a0b1+a1b0 on multi-value signals are disclosed. Also an efficient method of processing large binary signals is disclosed.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: July 14, 2009
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20090172501
    Abstract: Methods and apparatus create codewords of n-state symbols having one of 3 or more states with n-state check symbols. Check symbols are created from independent expressions. Codewords are associated with a matrix for detection of one or more symbols in error and the location of such symbols in error. Symbols in error are reconstructed from symbols not in error, error syndromes and check symbols not in error. Deliberately created errors that can be corrected are used as nuisance errors.
    Type: Application
    Filed: March 10, 2009
    Publication date: July 2, 2009
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7548092
    Abstract: An n-valued switch with n?2, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances of a physical phenomenon, an instance representing a state. N-valued inverters are also disclosed. Different types of signals are disclosed, including optical signals with different wavelengths, electrical signals with different frequencies and signals represented by a presence of a material. A kit including an n-valued switch is also disclosed.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: June 16, 2009
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7365576
    Abstract: A switching model to create stable binary sequential devices comprised of one or more logic functions with feedback of which an output signal is uniquely related to an input signal is applied to possible binary logic functions. Static latches of commutative and non-commutative binary functions are designed by using the switching model. Latches can be realized by individually controlled gates sometimes with inverters. Optical and electro-optical latches are disclosed. The application of transmission gates to realize latches is also disclosed.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: April 29, 2008
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7355444
    Abstract: Gates or switches for use in circuits implementing ternary and multi-value functions are disclosed. The gates can be optical, mechanical or electrical. The gates can conduct or not conduct when a control input assumes one of multiple states, or when a control input assumes two or more of multiple states. Circuits and methods for implementing ternary and multi-value functions are also disclosed. Corrective design techniques that can be used when a logic expression is incorrectly realized are also disclosed. Circuits that use inverters and gates to realize logic expressions are also provided.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: April 8, 2008
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7277030
    Abstract: Methods and apparatus for coding binary and multi-value sequences into higher value sequences are disclosed. Correlation methods for comparing lower-value sequences by first coding to higher value sequences and then calculating a correlation number are also disclosed. Methods and apparatus for resetting the coding rule during multi-value coding are also disclosed.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: October 2, 2007
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20070110229
    Abstract: Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described.
    Type: Application
    Filed: January 2, 2007
    Publication date: May 17, 2007
    Applicant: Ternarylogic, LLC
    Inventor: Peter Lablans
  • Patent number: 7218144
    Abstract: Gates or switches for use in circuits implementing ternary and multi-value functions are disclosed. The gates can be optical, mechanical or electrical. The gates can conduct or not conduct when a control input assumes one of multiple states, or when a control input assumes two or more of multiple states. Circuits and methods for implementing ternary and multi-value functions are also disclosed. Corrective design techniques that can be used when a logic expression is incorrectly realized are also disclosed. Circuits that use inverters and gates to realize logic expressions are also provided.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: May 15, 2007
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7002490
    Abstract: Ternary (3-value) and higher, multi-value digital scramblers/descramblers in digital communications. The method and apparatus of the present invention includes the creation of ternary (3-value) and higher value truth tables that establish ternary and higher value scrambling functions which are its own descrambling functions. The invention directly codes by scrambling ternary and higher-value digital signals and directly decodes by descrambling with the same function. A disclosed application of the invention is the creation of composite ternary and higher-value scrambling devices and methods consisting of single scrambling devices or functions combined with ternary or higher value shift registers. Another disclosed application is the creation of ternary and higher-value spread spectrum digital signals. Another disclosed application is a composite ternary or higher value scrambling system, comprising an odd number of scrambling functions and the ability to be its own descrambler.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: February 21, 2006
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans