Patents Assigned to Tetramem Inc.
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Patent number: 11522555Abstract: In accordance with some embodiments of the present disclosure, an apparatus including a crossbar circuit is provided. The crossbar circuit may include a plurality of cross-point devices with programmable conductance, a transimpedance amplifier (TIA), and an analog-to-digital converter (ADC). The TIA is configured to produce an output voltage based on an input current corresponding to a summation of current from a first plurality of the cross-point devices. The ADC is configured to generate a digital output corresponding to a digital representation of the output voltage of the TIA. To generate the digital output, the ADC is to generate, using a comparator, a first plurality of bits (e.g., MSBs) of the digital output by performing a coarse conversion process and a second plurality of bits (e.g., LSBs) of the digital output by performing a fine conversion process on a sample-and-hold voltage produced in the coarse conversion process.Type: GrantFiled: June 14, 2021Date of Patent: December 6, 2022Assignee: TetraMem Inc.Inventors: Ning Ge, Wenbo Yin
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Publication number: 20220367804Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, an RRAM device includes: a first electrode including a metal nitride; a second electrode comprising a first conductive material; and a switching oxide layer positioned between the first electrode and the second electrode. The switching oxide layer includes at least one transition metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and/or tantalum nitride. The first electrode does not include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc.Type: ApplicationFiled: June 17, 2022Publication date: November 17, 2022Applicant: TetraMem Inc.Inventors: Minxian Zhang, Mingche Wu, Ning Ge
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Patent number: 11495638Abstract: Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a first NMOS transistor; a second PMOS transistor; and an RRAM device. The first NMOS transistor and the second PMOS transistor are in parallel as a pair, wherein the pair connects in series with the RRAM device. The apparatus may further include an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal.Type: GrantFiled: August 25, 2019Date of Patent: November 8, 2022Assignee: TETRAMEM INC.Inventors: Wenbo Yin, Ning Ge
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Publication number: 20220320430Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. A method for fabricating resistive random-access memory (RRAM) device may include fabricating, on a first electrode of the RRAM device, a first interface layer comprising a first discontinuous film of a first material; fabricating, on the first interface layer, a switching oxide layer comprising at least one transition metal oxide; fabricating a second interface layer on the switching oxide layer; and fabricating a defect engineering layer on the second interface layer. The first material is more chemically stable than the at least one transition metal oxide. The defect engineering layer includes a layer of Ti in some embodiments.Type: ApplicationFiled: April 8, 2022Publication date: October 6, 2022Applicant: TetraMem Inc.Inventors: Minxian Zhang, Ning Ge
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Publication number: 20220284956Abstract: Aspects of the present disclosure provides a crossbar array circuit including: a crossbar array; a digital-to-analog converter (DAC) configured to receive an input signal to be applied to the crossbar array; a large input resistance connected to the DAC and the crossbar array; and an analog-to-digital converter (ADC) configured to generate output signals of the crossbar array circuit. The crossbar array includes a plurality of cross-point devices connecting a plurality of word lines and a plurality of bit lines. In some embodiments, the crossbar array circuit includes a large output resistance connected to the crossbar array.Type: ApplicationFiled: March 23, 2022Publication date: September 8, 2022Applicant: TetraMem, Inc.Inventors: Miao Hu, Ning Ge
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Patent number: 11410025Abstract: Systems and methods for implementing a multi-layer neural network using crossbar arrays are disclosed. In some implementations, an apparatus comprises: a plurality of first devices, a plurality of second devices, and a plurality of first flow controllers connecting the plurality of first devices and the plurality of second devices. Each flow controller in the plurality of first flow controllers is independently controlled from other flow controller in the plurality of first flow controllers. In some implementations, the apparatus further comprises: a plurality of third devices; a plurality of second flow controllers connecting the plurality of second devices and the plurality of third devices; and a first common ground line separating the plurality of first flow controllers and the plurality of second flow controllers. Each of the plurality of second flow controllers is independent of each of the plurality of first flow controllers.Type: GrantFiled: September 7, 2018Date of Patent: August 9, 2022Assignee: TetraMem Inc.Inventor: Ning Ge
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Patent number: 11388356Abstract: Technologies relating to AI fusion pixel sensor for MLP using active pixel sensors with memristors are disclosed. An example apparatus includes: many of active pixel sensors, wherein each active pixel sensors includes: a photodiode configured to receive image signal; a transfer gate; a selector controller; a reset controller; a voltage readout end; a first 1T1R cell, a second 1T1R cell, and a third 1T1R cell connected to the voltage readout end; and a first current readout end, a second current readout end, and a third current readout end connected to the first 1T1R cell, the second 1T1R cell, and the third 1T1R cell respectively; a first total current readout end, a second total current readout end, and a third total current readout end, whose total current equals the sum of the currents of all current readout ends in each active pixel sensors.Type: GrantFiled: April 12, 2021Date of Patent: July 12, 2022Assignee: TetraMem Inc.Inventors: Wenbo Yin, Ning Ge
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Publication number: 20220216399Abstract: Technologies relating to crossbar array circuits with proton-based two-terminal volatile memristive devices are disclosed. An example apparatus includes a first bottom conductive layer, a capacitor oxide layer formed on the first bottom conductive layer, a second bottom conductive layer formed on the capacitor oxide layer, a second oxide layer formed on the second bottom conductive layer, and a proton reservoir layer formed on the second oxide layer. In some embodiments, the second bottom conductive layer is H-doped. In some embodiments, a conductance of the second oxide layer is modulated by H-dopant.Type: ApplicationFiled: January 20, 2022Publication date: July 7, 2022Applicant: TETRAMEM INC.Inventor: Ning Ge
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Patent number: 11328772Abstract: Methods of using large output resistance with adjusted conductance mapping value to reduce the current in crossbar array circuit are disclosed. An example method of simulating a crossbar array circuit having a crossbar array, includes steps of: S1. testing the crossbar array; S2. calibrating a simulation model; S3. simulating the crossbar array with the simulation model, wherein a simulation result is generated after the S3; S4. determining a fixed ratio of ideal current from the simulation result; S5. adjusting conductance mapping value to let the crossbar array pass the fixed ratio of ideal current and generating a conductance matrix; S6. programming the conductance matrix to the crossbar array; S7. passing an input signal to the crossbar array and generating a computing result; and S8. checking the quality of computing results.Type: GrantFiled: July 6, 2020Date of Patent: May 10, 2022Assignee: TetraMem, Inc.Inventors: Miao Hu, Ning Ge
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Patent number: 11322683Abstract: Technologies relating to crossbar array circuits with proton-based two-terminal volatile memristive devices are disclosed. An example apparatus includes: a first bottom conductive layer, a first switching oxide layer formed on the first bottom conductive layer, a first top conductive layer formed on the first switching oxide layer, an intermediate layer formed on the first top conductive layer, a second bottom conductive layer formed on the intermediate layer, a second oxide layer whose conductance can be modulated by H-dopant formed on the second bottom conductive layer; and a proton reservoir layer formed on the second oxide layer, wherein the second bottom conductive layer is H-doped.Type: GrantFiled: February 21, 2020Date of Patent: May 3, 2022Assignee: TetraMem, Inc.Inventor: Ning Ge
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Publication number: 20220130902Abstract: Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a first NMOS transistor; a second PMOS transistor; and an RRAM device. The first NMOS transistor and the second PMOS transistor are in parallel as a pair, wherein the pair connects in series with the RRAM device. The apparatus may further include an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal.Type: ApplicationFiled: August 25, 2019Publication date: April 28, 2022Applicant: TETRAMEM INC.Inventors: Wenbo Yin, Ning Ge
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Patent number: 11283014Abstract: Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.Type: GrantFiled: August 28, 2019Date of Patent: March 22, 2022Assignee: TETRAMEM INC.Inventors: Minxian Zhang, Ning Ge
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Patent number: 11283018Abstract: Technologies relating to RRAM-based crossbar array circuits with increase temperature stability are disclosed. An example apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; and a top electrode formed on the filament forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer when applying a switching voltage upon the filament forming layer, and wherein a material of the filament includes nitrogen-doped Ta2O5, Ta2N/Ta2O5, or TaNyOz.Type: GrantFiled: March 27, 2019Date of Patent: March 22, 2022Assignee: TETRAMEM INC.Inventors: Ning Ge, Minxian Zhang
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Publication number: 20220077389Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. An RRAM device may include a first electrode, a first interface layer fabricated on the first electrode; a switching oxide layer fabricated on the first interface layer; and a second electrode fabricated on the switching oxide layer. The switching oxide layer includes a transition metal oxide. The first interface layer includes a discontinuous film of a first material that is more chemically stable than the transition metal oxide. The RRAM device may further include a second interface layer positioned between the switching oxide layer and the second electrode. The second interface layer includes a discontinuous film of a second material that is more chemically stable than the transition metal oxide. The second electrode may include multiple electrode components that may include an alloy, a first layer of a first metallic material, and/or a second layer of a second metallic material.Type: ApplicationFiled: November 15, 2021Publication date: March 10, 2022Applicant: TetraMem Inc.Inventors: Minxian Zhang, Ning Ge
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Publication number: 20220013720Abstract: Switching oxide engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. An apparatus, in some implementations, includes: a substrate; a bottom electrode formed on the substrate; a switching oxide stack formed on the bottom electrode. The switching oxide stack includes one or more base oxide layers and one or more discontinuous oxide layers alternately stacked; An apparatus further includes a top electrode formed on the switching oxide stack. The base oxide layer includes TaOx, HfOx, TiOx, ZrOx, or a combination thereof. The discontinuous oxide layer includes Al2O3, SiO2, Si3N4, Y2O3, Gd2O3, Sm2O3, CeO2, Er2O3, or the combination thereof.Type: ApplicationFiled: July 7, 2020Publication date: January 13, 2022Applicant: TETRAMEM INC.Inventors: Minxian Zhang, Ning Ge
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Publication number: 20220006008Abstract: Interface engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. An apparatus, in some implementations, includes: a substrate; a bottom electrode formed on the substrate; a first geometric confining layer formed on the bottom electrode. The first geometric confining layer comprises a first plurality of pin-holes. The apparatus further comprises a base oxide layer formed on the first geometric confining layer and connected to a first top surface of the bottom electrode via the first pin-holes; and a top electrode formed on the base oxide layer. The base oxide layer comprises one of: TaOx, HfOx, TiOx, ZrOx, or a combination thereof; the first geometric confining layer comprises Al2O3, SiO2, Si3N4, Y2O3, Gd2O3, Sm2O3, CeO2, Er2O3, or a combination thereof.Type: ApplicationFiled: July 6, 2020Publication date: January 6, 2022Applicant: TETRAMEM INC.Inventors: Minxian Zhang, Ning Ge
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Publication number: 20220005526Abstract: Methods of using large output resistance with adjusted conductance mapping value to reduce the current in crossbar array circuit are disclosed. An example method of simulating a crossbar array circuit having a crossbar array, includes steps of: S1. testing the crossbar array; S2. calibrating a simulation model; S3. simulating the crossbar array with the simulation model, wherein a simulation result is generated after the S3; S4. determining a fixed ratio of ideal current from the simulation result; S5. adjusting conductance mapping value to let the crossbar array pass the fixed ratio of ideal current and generating a conductance matrix; S6. programming the conductance matrix to the crossbar array; S7. passing an input signal to the crossbar array and generating a computing result; and S8. checking the quality of computing results.Type: ApplicationFiled: July 6, 2020Publication date: January 6, 2022Applicant: TETRAMEM INC.Inventors: Miao Hu, Ning Ge
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Patent number: 11217630Abstract: Technologies relating to implementing memristor crossbar arrays using non-filamentary RRAM cells are disclosed. In some implementations, an apparatus comprises: a first row wire; a first column wire; a non-filamentary RRAM; and an access control device. The non-filamentary RRAM and the access control device are serially connected; the non-filamentary RRAM and the access control device connect the first row wire with the first column wire. The non-filamentary RRAM and the access control device may form a cross-point device. The cross-point device may be less than 40×40 nm2. A set current of the non-filamentary RRAM may be no more than 10 ?A; and a reset current of the non-filamentary RRAM is no more than 10 ?A. The access control device may comprise a transistor or a selector.Type: GrantFiled: April 24, 2019Date of Patent: January 4, 2022Assignee: TetraMem Inc.Inventors: Minxian Zhang, Ning Ge
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Patent number: 11151289Abstract: Systems and methods for providing a non-rewritable code comparator using a memristor and a serial resistor are disclosed. An example apparatus comprises: a plurality of first terminals; a plurality of second terminals; and a plurality of two-terminal device pairs formed between the plurality of first terminals and the plurality of second terminals. Each two-terminal device pair in the plurality of two-terminal device pairs include at least one memristor and at least one resistor; each two-terminal device pair is configured to be switched to a subsequent state once and only once. In some implementations, a two-terminal device pair is configured to remain in the subsequent state regardless of whether an input signal to the apparatus matches a reference signal to the apparatus.Type: GrantFiled: November 2, 2018Date of Patent: October 19, 2021Assignee: TetraMem Inc.Inventor: Ning Ge
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Publication number: 20210320148Abstract: Technologies relating to crossbar array circuits with parallel grounding lines are disclosed. An example crossbar array circuit includes: a word line; a bit line; a first selector line; a grounding line; a first transistor including a first source terminal, a first drain terminal, a first gate terminal, and a first body terminal; and an RRAM device connected in series with the first transistor. The grounding line is connected to the first body terminal and is grounded and the grounding line parallel to the bit line. The first selector line is connected to the first gate terminal. In some implementations, the RRAM device is connected between the first transistor via the first drain terminal and the word line, and the first source terminal is connected to the bit line.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Applicant: TetraMem Inc.Inventor: Ning Ge