Abstract: A system includes a non-programmable bus master. The non-programmable bus master includes a memory protection unit (MPU) to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions, and hardware logic. The hardware logic executes a first task and a second task. The tasks generate transactions and the hardware logic switches between executing the first and second tasks. The hardware logic also causes the MPU to operate in the first configuration when the hardware logic executes the first task and causes the MPU to operate in the second configuration when the hardware logic executes the second task.

Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits.

Abstract: A method is provided. A first enable signal is asserted so as to enable a first driver, where the first driver has a first output and a first parasitic capacitance. A second enable signal is asserted so as to enable a second driver, where the second driver has a second output and a second parasitic capacitance. The first and second outputs are coupled together by a switching network when the second driver is enabled. Pulses from complementary first and second radio frequency (RF) signals are applied to the first driver, where there is a first set of free-fly intervals between consecutive pulses from the first and second RF signals, and pulses from complementary third and fourth RF signals are applied to the second driver, wherein there is a second set of free-fly interval between consecutive pulses from the third and fourth RF signals.

Abstract: A system and method for reducing pulse width modulation contouring artifacts. Each input intensity value is translated to at least one non-binary bit pattern for display. Many of the input intensity values are translated to at least two alternate non-binary bit patterns. The alternate codes are used to smooth the transition between intensity codes as major bits are turned on. The smoothing occurs by the gradual transition from codes that do not use the major bit to codes that do use the major bit. Typically the alternate codes are selected based on the location of the pixel in a spatial pattern (100) and the alternate codes are spatially alternated from one pixel (102) to the next (104). Other embodiments temporally alternate the codes from one period—typically a frame period—to the next. Still other embodiments alternate the codes both spatially and temporally.

Abstract: An output stage for an amplifier is provided. The amplifier generally provides for compensation of an error current generated by the base-collector (or gate-drain) capacitance of a common base (or gate) amplifier transistor. The stage accomplishes this by utilizing a three transistor Wilson current mirror to combine the error current with a mirrored bias current to reduce the load current on the common base (or gate) amplifier transistor.

Abstract: An apparatus to power and dim LEDs is provided. The apparatus generally comprises a boost converter having an output node, a regulator node, a sensing network, and an impedance network. LEDs, which are coupled in series with one another, are coupled between the output node and the impedance network of the boost converter. A zener diode is coupled to the output node and coupled to the sensing network, and a dimming circuit is coupled to the boost converter. The dimming circuit includes a diode coupled to the impedance network, a switch coupled between the diodes and ground (which receives the signal for dimming the plurality of LEDs), and a network coupled to the regulator node and to the node between the second diode and the second switch.

Abstract: Enabling non-interoperability among transceivers of devices. A method includes transmitting a signal at a predefined symbol rate by a first transceiver of a first device of a first plurality of devices. The predefined symbol rate is unique for each transceiver of each device of the first plurality of devices. The method also includes detecting the signal by a second transceiver of a second device of a second plurality of devices. The second transceiver has a symbol rate similar to the predefined symbol rate.

Abstract: A system 100 for scan testing at least two substantially identical modules 140 and 150 within an integrated circuit is provided. The system 100 includes a first module 140 to receive and process scan input and produce a first scan output. The system 100 includes a second module 150 substantially similar to the first module 140. The second module 150 receives and processes scan input and produces a second scan output. The system 100 also includes a first component 180 to receive the first and second scan outputs and to produce a first output. The first output is used to determine whether the first and second modules 140 and 150 are functioning properly.

Abstract: A socket for receiving a line of contact pins is formed of modules connected together. The modules have three, four or five pin receiving openings and are joined to one another by dovetail connectors to form an elongated body having the desired number of pin receiving openings. Contacts are provided in the pin receiving openings to electrically connect with the pins. The modules have a ledge on which rests a work surface.

Abstract: A detector (55) and method for detecting a synchronization servo mark (SSM) in a data stream of mass data storage device (10) has a matched filter (56) to receive the data stream. The filter (56) produces a maximum output when the SSM is applied. A delay element receives (64) the matched filter output to produce a delay element output (72). When the delay element output (72) is greater than a predetermined threshold value (Vth) and is larger than the output value (74), the (SSM) is in a current time location. When the “D” element output (72) is greater than the predetermined threshold value (Vth) and less than the output value, the SSM is in the next time location. The threshold may be established to be less than maximum if the phase of the SSM is within a predetermined phase range.

Abstract: A wireless transmitter (TX1). The transmitter comprises circuitry for providing a plurality of control (CONTROL) bits and circuitry for providing a plurality of user (USER) bits. The transmitter also comprises circuitry for modulating (16) the plurality of control bits and the plurality of user bits into a stream of complex symbols and circuitry (18) for converting the stream of complex symbols into a parallel plurality of complex symbol streams. The transmitter also comprises circuitry (20) for performing an inverse fast Fourier transform on the parallel plurality of complex symbol streams to form a parallel plurality of OFDM symbols and circuitry (22) for converting the parallel plurality of OFDM symbols into a serial stream of OFDM symbols. Each OFDM symbol in the serial stream of OFDM symbols comprises a plurality of data points, and selected (SF2.x) OFDM symbols in the serial stream of OFDM symbols carry modulation information (AMOD).

Abstract: A high speed digital static shift register includes a series-connected pair of resonant tunneling diodes (RTDs) 22, 24 to achieve a bistable operating state. A clocked switch 20 provides the means of setting the binary state of this bistable pair. In order for one bistable pair to drive a following pair, a method of providing isolation and gain using a buffer amplifier 26 between the two pairs of RTDs is also provided. In one embodiment, the buffer amplifier comprises enhancement FET 30 and depletion load FET 28.

Abstract: A display system with a pointer that is not restricted by wires or sensors. The display uses a spatial light modulator (14) for projecting an image on the screen (20). During a time period when all of the cells of the modulator (14) are in the same state, a cursor projected onto the screen by the pointer is reimaged from the screen to a detector (26), which translates the cursor image into signals for a central processing unit (38). The central processing unit (38) then directs the system as to what tasks are being dictated by the cursor.

Abstract: An ultraclean evaporation system which includes a vessel formed of a fluoropolymer inert to hydrogen peroxide and having an impurity level less than the impurity level of samples to be analyzed therein, preferably perfluoroalkoxy (PFA). A radiant heater is spaced from the vessel for uniformly heating the contents of the vessel. A shield, manufactured of aluminum and coated with a fluoropolymer encases the vessel alone or in conjunction with the heater. An inert gas supply is coupled to the vessel with a coupler of fluoropolymer inert to hydrogen peroxide, preferably PFA. An output is provided from the vessel formed of a fluoropolymer inert to hydrogen peroxide, preferably PFA. An orifice is provided which is formed of a fluoropolymer inert to hydrogen peroxide, preferably PFA, for controlling the flow rate of the inert gas supply. The tubing has a length of at least about 3 meters. The vessel has a side wall and a bottom forming a corner and is disposed so that the corner is the lowest region of the vessel.