Abstract: A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.

Abstract: A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.

Abstract: An overcurrent detector that includes a sense transistor connected to a sense resistor, a second transistor matched to the sense transistor and connected in parallel to a second resistor, and a voltage comparator coupled to the sense transistor and second resistor. The sense transistor is configured to connect in a same gate and source connection with a driver output transistor. The second transistor and second resistor are configured to receive a current reference and generate a voltage reference. The voltage comparator is configured to compare the voltage reference with a voltage drop across the sense resistor.

Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

Abstract: An apparatus comprises a differential equalizer having: a) a first differential input, b) a second differential input, c) a first differential output, and d) a second differential output; a frequency detector coupled to the first and second differential inputs; an amplifier coupled to a first differential output and a second differential output of the differential equalizer; and a logical combiner having a first input coupled to an output of the frequency detector and an output coupled to a control input of the amplifier, wherein the logical combiner can mask at least one received de-emphasis parameter.

Abstract: A method of etching a ferroelectric capacitor stack structure including conductive upper and lower plates with a ferroelectric material, such as lead-zirconium-titanate (PZT), therebetween, with each of these layers defined by the same hard mask element. The stack etch process involves a plasma etch with a fluorine-bearing species as an active species in the etch of the conductive plates, and a non-fluorine-bearing chemistry for etching the PZT ferroelectric material. An example of the fluorine-bearing species is CF4. Endpoint detection can be used to detect the point at which the upper plate etch reaches the PZT, at which point the gases in the chamber are purged to avoid etching the PZT material with fluorine. A steeper sidewall angle for the capacitor structure can be obtained.

Abstract: A symbol modulation system applicable to a body area network is disclosed herein. The symbol modulation system includes a symbol mapper. The symbol mapper is configured to determine a time within a predetermined symbol transmission interval at which a transmission representative of the symbol will occur. The time is determined based on a value of a symbol and a value of a time-hopping sequence. The time is selected from a plurality of symbol value based time slots, and a plurality of time-hopping sequence sub-time-slots within each symbol value based time slot. The symbol mapper is configured to generate a single guard interval within the symbol transmission interval. The single guard interval is positioned to terminate the symbol transmission interval.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: A method for designing a mask set including at least one mask includes the implementation of at least one design rule from a set of design rules. The design rules include rules relating to allowable spacing between adjacent features, overlap of features defined by different masks in the mask set, and other characteristics of the mask set.

Abstract: A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.

Abstract: System and method for utilizing two prisms spatially separated is provided. The two prisms spatially separated allows the two prisms typically found in a TIR optical relay system to be spatially separated. In an embodiment, one or more optical relay lenses are interposed between the two prisms. The prism positioned on the object side may be integrated into one or more of the optical relay lenses, thereby further simplifying the optical relay design. In another embodiment, the one or more optical relay lenses may have an optical axis that is offset from the optical axis of incoming light to cause a pupil shift. An aspherical lens may be included to correct for the pupil shift and create a more uniform illumination image.

Abstract: Navigating trace data. A traced program, or the operating system responsible for the traced program, writes index values to a particular hardware location, which index values become part of the trace data by operation of hardware devices in the target system. A debug-trace program (executed either in an attached host computer or as an embedded debugger) uses the index values to assist the user of the debug-trace program in navigating to particular portions of the trace data based on the index values.

Abstract: In accordance with one embodiment, a method for emulating the color performance of a display system includes determining an expected first color gamut of the display system. Display data is converted into a format that emulates the first color gamut. The converted display data is displayed by a different display system having an expected second color gamut different than the expected first color gamut.

Abstract: A reference voltage circuit having an open-loop buffer driven by a matching buffer included within a closed-loop, generates a stable differential or single-ended voltage while minimizing signal-dependent short-term and long-term drift. The open-loop buffer may be a replica of the closed-loop buffer, reducing the effect of a signal coupled on the voltage reference lines. The reference voltage circuit may be adapted for a switched capacitor ADC.

Abstract: A bridge controller controls the data flow to/from a USB bus to/from an ATA/ATAPI drive, such as an ATA hard drive or ATAPI CD or DVD drive. The bridge controller has a state machine which receives the CBW in a background mode in real time as the packet is being transferred to the bridge controller. The state machine uses the CBW to set up the data transfer. The bridge controller also has a programmable processor which is coupled to the CBW once it is received in a buffer memory. The programmable processor makes changes in the set up of the receiving device for the transfer, if needed, and initiates the data transfer.

Abstract: A electrostatic sensing device for sensing a voltage from a electrostatic device, includes a first actuator having a first membrane and a first electrode, the first membrane being moveable and a second actuator having a second membrane and a second electrode, the second membrane being moveable. Additionally, a control device controls the first actuator and the second actuator to alternatively charge the first actuator with a first charge and the second actuator with a second charge, and a circuit outputs a first voltage linearly based on the first charge and a second voltage linearly based on the second charge.

Abstract: A static antenna tuning and antenna voltage measurement circuit (40) includes antenna voltage conversion circuitry (44) for converting a voltage signal (42) to a measurement signal representative of transmitter/receiver antenna (16) operation. Voltage signal (42) arises from transmitter/receiver antenna (16) transmitting or receiving a recognition signal (S1, S2). Comparator circuitry (48, 50, 52) compares the measurement signal to a predetermined optimal transmitter/receiver antenna operation signal.

Abstract: A level shift is provided between a first level and a second level for a first and second compensatory signal. Power supply variations are measured and the levels are compensated for these power supply variations so that the power supply does not affect the first and second levels.

Abstract: This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.