Abstract: Described are computer-based methods and apparatuses, including computer program products, for non-disruptive data path modification using target mobility. A management server is in communication with a switching fabric. The switching fabric is in communication with a host and a data storage element. The management server creates a takeover target based on a primary target, where the primary target is part of a virtual data path between the host and the data storage. The switching fabric, through the direction of the server, modifies metadata associated with the virtual data path to expose the takeover target so that the takeover target becomes part of the virtual data path. The management server unexposes the primary target so that the primary target is no longer part of the virtual data path. The delay between exposing the takeover target and unexposing the primary target is sufficiently small to prevent an error condition from occurring at the host.

Abstract: Methods and apparatuses for optimizing the performance of a storage system comprise a FLASH storage system, a hard drive storage system, and a storage controller. The storage controller is adapted to receive READ and WRITE requests from an external host, and is coupled to the FLASH storage system and the hard drive storage system. The storage controller receives a WRITE request from an external host containing data and an address, forwards the received WRITE request to the FLASH storage system and associates the address provided in the WRITE request with a selected alternative address, and provides an alternative WRITE request, including the selected alternative address and the data received in the WRITE request, to the hard drive storage system, wherein the alternative address is selected to promote sequential WRITE operations within the hard drive storage system.

Abstract: A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.

Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using page stripes and auxiliary protection stripes. The controller stores the data in a manner such that the pages making up each page stripe include a plurality of data pages and at least one data protection page and the pages making up each auxiliary protection stripe include a plurality of data pages and an auxiliary protection page. At least a plurality of data pages are within one page stripe and one auxiliary protection stripe such that each data page is protected both by a data protection page in the page stripe and an auxiliary protection page in the auxiliary protection stripe.

Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using page stripes and auxiliary protection stripes. The controller stores the data in a manner such that the pages making up each page stripe include a plurality of data pages and at least one data protection page and the pages making up each auxiliary protection stripe include a plurality of data pages and an auxiliary protection page. At least a plurality of data pages are within one page stripe and one auxiliary protection stripe such that each data page is protected both by a data protection page in the page stripe and an auxiliary protection page in the auxiliary protection stripe.

Abstract: Methods and apparatuses provide a clocked digital device having dynamically adjustable operating characteristics. The digital device comprises a digital clock management (“DCM”) circuit in which the amount of delay between receipt of an active edge of a clock signal at the input of the DCM circuit and appearance of an active edge of another clock signal at the output of the DCM circuit depends on a phase adjustment signal applied to the DCM circuit's phase adjust input. A phase adjustment circuit provides the phase adjustment signal to the DCM circuit's phase adjust input for controlling the amount of the delay between the clock signal at the input of the DCM circuit and the clock signal at the output of the DCM circuit.

Abstract: An active low-pass current filter apparatus and method reduces conducted emissions above a predefined cutoff frequency at high power levels. The apparatus and method use a bidirectional DC-DC converter to minimize current fluctuations on a power lead that may result in conducted emissions above the predefined cutoff frequency. The bidirectional DC-DC converter absorbs current from the power lead and feeds current to the load lead as needed to compensate for the current fluctuations on the power lead. Power to the DC-DC converter is provided by a separate auxiliary power source. A monitoring circuit compares the voltage level of the auxiliary power source to a reference voltage and compensates for variations in the voltage level of the auxiliary power source without interfering with the suppression of the conducted emissions.

Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using page stripes and auxiliary protection stripes. The controller stores the data in a manner such that the pages making up each page stripe include a plurality of data pages and at least one data protection page and the pages making up each auxiliary protection stripe include a plurality of data pages and an auxiliary protection page. At least a plurality of data pages are within one page stripe and one auxiliary protection stripe such that each data page is protected both by a data protection page in the page stripe and an auxiliary protection page in the auxiliary protection stripe.

Abstract: Methods and apparatuses provide a clocked digital device having dynamically adjustable operating characteristics. The digital device comprises a digital clock management (“DCM”) circuit in which the amount of delay between receipt of an active edge of a clock signal at the input of the DCM circuit and appearance of an active edge of another clock signal at the output of the DCM circuit depends on a phase adjustment signal applied to the DCM circuit's phase adjust input. A phase adjustment circuit provides the phase adjustment signal to the DCM circuit's phase adjust input for controlling the amount of the delay between the clock signal at the input of the DCM circuit and the clock signal at the output of the DCM circuit.

Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of using variable size page stripes in the memory system. The controller is configured to store data such that each page stripe comprises a plurality of data pages, with each data page in the page stripe being stored in a different FLASH memory chip. The controller is also configured to maintain one or more buffers containing information reflecting blocks of memory within the FLASH memory chips that have been erased and are available for information storage, and to dynamically determine the number of data pages to be included in a page stripe based on the information in the one or more buffers such that a first page stripe and a second page stripe can have different numbers of data pages.

Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using different size page stripes. The controller is configured to store data in FLASH memory devices in the form of page stripes, each page stripe comprising a plurality of pages of information, each page of information being stored in a different FLASH memory chip. The controller stores the data in a manner such that the pages making up each page stripe includes a plurality of data pages and at least one data protection page. In one implementation, the page stripes stored by the controller include a first page stripe having N data pages and one data protection page, and a second page stripe having M data pages and one data protection page, where N is an integer greater than three and M is an integer less than N.

Abstract: Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string.

Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system utilizing modified or extra FLASH memory cells.

Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of adapting to the failure of one or more FLASH memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different FLASH memory device. The controller also detects failure of a FLASH memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed FLASH memory device.

Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using page stripes and auxiliary protection stripes. The controller stores the data in a manner such that the pages making up each page stripe include a plurality of data pages and at least one data protection page and the pages making up each auxiliary protection stripe include a plurality of data pages and an auxiliary protection page. At least a plurality of data pages are within one page stripe and one auxiliary protection stripe such that each data page is protected both by a data protection page in the page stripe and an auxiliary protection page in the auxiliary protection stripe.

Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.

Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of using variable size page stripes in the memory system. The controller is configured to store data such that each page stripe comprises a plurality of data pages, with each data page in the page stripe being stored in a different FLASH memory chip. The controller is also configured to maintain one or more buffers containing information reflecting blocks of memory within the FLASH memory chips that have been erased and are available for information storage, and to dynamically determine the number of data pages to be included in a page stripe based on the information in the one or more buffers such that a first page stripe and a second page strip can have different numbers of data pages.

Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.

Abstract: Described are methods, systems, and apparatus, including computer program products, for achieving distributed asynchronous ordered replication. Distributed asynchronous ordered replication includes creating a first journal for a first set of I/O data, creating a second journal for a second set of I/O data, and temporarily preventing committal, of the second set of I/O data until the second journal is created. In some examples, the first and second journals comprise entries. The entries of the first and second journals include counter values. The entries of the first journal typically have a different counter value than the entries of the second journal.

Abstract: The invention is directed to a system and method for writing data from a non-volatile storage means to a volatile memory module within a solid state disk system, upon start-up. The system preferably uses a control module coupled to a memory module and storage means. The control module preferably maintains a load priority queue for recording data requests made by a computer network connected to the system. During start up of the solid state disk system, the control module examines the load priority to queue and determines if any of the data requests are applicable to data segments already loaded during the startup process.