Patents Assigned to TFPD Corporation
-
Publication number: 20070081108Abstract: An array substrate for a flat-panel display device and manufacturing method thereof, enabling a reliable repairing of a wire breakage within a pixel area, irrespective of nature of the wire breakage, especially irrespective of nature, dimensions and shape of a foreign matter causing the wire breakage. For example, when the wire breakage due to foreign matter is formed on a signal line, the foreign matter is removed and then a bypass wire detouring the wire breakage is formed by laser CVD technique. On beforehand, a rectangular cutout is formed on a neighboring pixel electrode by laser irradiation; and contact holes for exposing upper faces of two wire parts of the signal line as separated by the wire breakage. After forming angled-C shaped bypass wire along edges of the cutout on the pixel electrode, a light insulator film is formed at inside of the bypass wire by laser CVD technique.Type: ApplicationFiled: March 24, 2003Publication date: April 12, 2007Applicant: TFPD CORPORATIONInventor: Ichiro Tsukada
-
Patent number: 7115913Abstract: A TFT array substrate used for a display device and a method of making the same are disclosed. A optically transparent thick resin insulation film 5 is formed on a base substrate and an upper contact hole 51 is perforated through the optically transparent thick resin insulation film 5. A lower contact hole 41 perforated through a gate insulation film 15 and patterning of an ITO film to make a transparent pixel electrode are then collectively carried out under a photoresist pattern 8. Where the photoresist pattern 8 is provided after making the ITO film, an aperture 81 is perforated closer to the center of the upper contact hole 51 at an end portion of a connecting line 14a for a pad and is smaller in diameter by a side etching size plus a margin than the upper contact hole.Type: GrantFiled: March 25, 2003Date of Patent: October 3, 2006Assignee: TFPD CorporationInventor: Hirotaka Shigeno
-
Patent number: 7042149Abstract: A circuit array substrate 10 includes pixel and connecting edge sections 80 and 90. Connecting edge section 90 is provided with edge portions 5a and shoulder portions 55 of transparent thin resin film 5 over which terminal pins 101 of tape carrier packages (TCP) 100 are disposed. Terminal pins 101 are connected to connecting pads 14 at their contact portions 103. Shoulder portions 55 prevent a coated photoresist film from being excessive in depth and residues of the photoresist film from being left in the foot of edge face 5a in the step of forming metal reflective pixel electrodes. Thus, no residue of the metal film exists after its etching treatment in that step so that no electrical short circuits are caused between connecting pads 14 and adjacent terminal pins 101.Type: GrantFiled: June 9, 2003Date of Patent: May 9, 2006Assignee: TFPD CorporationInventor: Hirotaka Shigeno
-
Patent number: 7021983Abstract: A circuit array substrate 10 includes pixel and connecting edge sections 80 and 90. Connecting edge section 90 is provided with edge portions 5a and shoulder portions 55 of transparent thin resin film 5 over which terminal pins 101 of tape carrier packages (TCP) 100 are disposed. Terminal pins 101 are connected to connecting pads 14 at their contact portions 103. Shoulder portions 55 prevent a coated photoresist film from being excessive in depth and residues of the photoresist film from being left in the foot of edge face 5a in the step of forming metal reflective pixel electrodes. Thus, no residue of the metal film exists after its etching treatment in that step so that no electrical short circuits are caused between connecting pads 14 and adjacent terminal pins 101.Type: GrantFiled: September 15, 2005Date of Patent: April 4, 2006Assignee: TFPD CorporationInventor: Hirotaka Shigeno
-
Publication number: 20060009108Abstract: A circuit array substrate 10 includes pixel and connecting edge sections 80 and 90. Connecting edge section 90 is provided with edge portions 5a and shoulder portions 55 of transparent thin resin film 5 over which terminal pins 101 of tape carrier packages (TCP) 100 are disposed. Terminal pins 101 are connected to connecting pads 14 at their contact portions 103. Shoulder portions 55 prevent a coated photoresist film from being excessive in depth and residues of the photoresist film from being left in the foot of edge face 5a in the step of forming metal reflective pixel electrodes. Thus, no residue of the metal film exists after its etching treatment in that step so that no electrical short circuits are caused between connecting pads 14 and adjacent terminal pins 101.Type: ApplicationFiled: September 15, 2005Publication date: January 12, 2006Applicant: TFPD CorporationInventor: Hirotaka Shigeno
-
Publication number: 20040008167Abstract: A circuit array substrate 10 includes pixel and connecting edge sections 80 and 90. Connecting edge section 90 is provided with edge portions 5a and shoulder portions 55 of transparent thin resin film 5 over which terminal pins 101 of tape carrier packages (TCP) 100 are disposed. Terminal pins 101 are connected to connecting pads 14 at their contact portions 103. Shoulder portions 55 prevent a coated photoresist film from being excessive in depth and residues of the photoresist film from being left in the foot of edge face 5a in the step of forming metal reflective pixel electrodes. Thus, no residue of the metal film exists after its etching treatment in that step so that no electrical short circuits are caused between connecting pads 14 and adjacent terminal pins 101.Type: ApplicationFiled: June 9, 2003Publication date: January 15, 2004Applicant: TFPD CorporationInventor: Hirotaka Shigeno
-
Publication number: 20030209726Abstract: A TFT array substrate used for a display device and a method of making the same are disclosed. A optically transparent thick resin insulation film 5 is formed on a base substrate and an upper contact hole 51 is perforated through the optically transparent thick resin insulation film 5. A lower contact hole 41 perforated through a gate insulation film 15 and patterning of an ITO film to make a transparent pixel electrode are then collectively carried out under a photoresist pattern 8. Where the photoresist pattern 8 is provided after making the ITO film, an aperture 81 is perforated closer to the center of the upper contact hole 51 at an end portion of a connecting line 14a for a pad and is smaller in diameter by a side etching size plus a margin than the upper contact hole.Type: ApplicationFiled: March 25, 2003Publication date: November 13, 2003Applicant: TFPD CorporationInventor: Hirotaka Shigeno